PIC16F877AT-E/L Microchip Technology, PIC16F877AT-E/L Datasheet - Page 121
![IC MCU FLASH 8KX14 W/AD 44-PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC16F877AT-E/L
Manufacturer Part Number
PIC16F877AT-E/L
Description
IC MCU FLASH 8KX14 W/AD 44-PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873A-ISO.pdf
(234 pages)
5.PIC16F873A-ISO.pdf
(6 pages)
6.PIC16F873A-ISO.pdf
(4 pages)
7.PIC16F873A-ISO.pdf
(6 pages)
8.PIC16F873A-ISO.pdf
(4 pages)
Specifications of PIC16F877AT-E/L
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-PLCC
For Use With
DVA16XL441 - ADAPTER DEVICE ICE 44PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873A-ISO PDF datasheet #4
- PIC16F873A-ISO PDF datasheet #5
- PIC16F873A-ISO PDF datasheet #6
- PIC16F873A-ISO PDF datasheet #7
- PIC16F873A-ISO PDF datasheet #8
- Current page: 121 of 234
- Download datasheet (5Mb)
10.2.3
When setting up an Asynchronous Reception with
address detect enabled:
• Initialize the SPBRG register for the appropriate
• Enable the asynchronous serial port by clearing
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
FIGURE 10-6:
2003 Microchip Technology Inc.
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
bit SYNC and setting bit SPEN.
F
OSC
RC7/RX/DT
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
Baud Rate Generator
x64 Baud Rate CLK
USART RECEIVE BLOCK DIAGRAM
SPBRG
and Control
Pin Buffer
SPEN
RSR<8>
ADDEN
ADDEN
RX9
RX9
Recovery
Interrupt
Data
or
64
16
CREN
Enable
Load of
Receive
Buffer
RCIF
RCIE
• Flag bit RCIF will be set when reception is
• Read the RCSTA register to get the ninth bit and
• Read the 8-bit received data by reading the
• If any error occurred, clear the error by clearing
• If the device has been addressed, clear the
RX9
complete, and an interrupt will be generated if
enable bit RCIE was set.
determine if any error occurred during reception.
RCREG register to determine if the device is
being addressed.
enable bit CREN.
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer and interrupt the
CPU.
Stop
MSb
RX9D
(8)
OERR
7
RSR Register
RCREG Register
8
PIC16F87XA
Data Bus
8
8
1
FERR
0
LSb
Start
FIFO
DS39582B-page 119
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