PIC16F877AT-E/L Microchip Technology, PIC16F877AT-E/L Datasheet - Page 74
![IC MCU FLASH 8KX14 W/AD 44-PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC16F877AT-E/L
Manufacturer Part Number
PIC16F877AT-E/L
Description
IC MCU FLASH 8KX14 W/AD 44-PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873A-ISO.pdf
(234 pages)
5.PIC16F873A-ISO.pdf
(6 pages)
6.PIC16F873A-ISO.pdf
(4 pages)
7.PIC16F873A-ISO.pdf
(6 pages)
8.PIC16F873A-ISO.pdf
(4 pages)
Specifications of PIC16F877AT-E/L
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-PLCC
For Use With
DVA16XL441 - ADAPTER DEVICE ICE 44PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873A-ISO PDF datasheet #4
- PIC16F873A-ISO PDF datasheet #5
- PIC16F873A-ISO PDF datasheet #6
- PIC16F873A-ISO PDF datasheet #7
- PIC16F873A-ISO PDF datasheet #8
- Current page: 74 of 234
- Download datasheet (5Mb)
PIC16F87XA
9.3.1
The MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register (SSPCON)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
• MSSP Shift Register (SSPSR) – Not directly
SSPCON and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON regis-
ter is readable and writable. The lower six bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 9-1:
DS39582B-page 72
(SSPBUF)
accessible
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
REGISTERS
SSPSTAT: MSSP STATUS REGISTER (SPI MODE) (ADDRESS 94h)
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
D/A: Data/Address bit
Used in I
P: Stop bit
Used in I
S: Start bit
Used in I
R/W: Read/Write bit information
Used in I
UA: Update Address bit
Used in I
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
R = Readable bit
- n = Value at POR
R/W-0
Note:
SMP
2
2
2
2
2
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
C mode only.
C mode only.
C mode only.
C mode only.
Polarity of clock state is set by the CKP bit (SSPCON1<4>).
R/W-0
CKE
R-0
D/A
W = Writable bit
‘1’ = Bit is set
R-0
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0
S
R/W
R-0
2003 Microchip Technology Inc.
x = Bit is unknown
R-0
UA
R-0
BF
bit 0
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