ATMEGA32-16PI Atmel, ATMEGA32-16PI Datasheet - Page 227
![IC AVR MCU 32K 16MHZ IND 40-DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA32-16PI
Manufacturer Part Number
ATMEGA32-16PI
Description
IC AVR MCU 32K 16MHZ IND 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32-16PI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32-16PI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Boundary-scan Chain
Boundary-scan
Specific JTAG
Instructions
EXTEST; $0
IDCODE; $1
SAMPLE_PRELOAD;
$2
2503Q–AVR–02/11
Figure 115. Reset Register
The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
Off-chip connections.
See
The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG
instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not
implemented, but all outputs with tri-state capability can be set in high-impedant state by using
the AVR_RESET instruction, since the initial state for all port pins is tri-state.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing
circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output
Data, and Input Data are all accessible in the scan chain. For Analog circuits having Off-chip
connections, the interface between the analog and the digital logic is in the scan chain. The con-
tents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-
register is loaded with the EXTEST instruction.
The active states are:
•
•
•
Optional JTAG instruction selecting the 32-bit ID-register as Data Register. The ID-register con-
sists of a version number, a device number and the manufacturer code chosen by JEDEC. This
is the default instruction after power-up.
The active states are:
•
•
Mandatory JTAG instruction for pre-loading the output latches and talking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-scan Chain is selected as Data Register.
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
Shift-DR: The Internal Scan Chain is shifted by the TCK input.
Update-DR: Data from the scan chain is applied to output pins.
Capture-DR: Data in the IDCODE-register is sampled into the Boundary-scan Chain.
Shift-DR: The IDCODE scan chain is shifted by the TCK input.
“Boundary-scan Chain” on page 229
External Reset Sources
From other Internal and
From
ClockDR · AVR_RESET
TDI
D
for a complete description.
Q
TDO
To
ATmega32(L)
Internal Reset
227
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