ATTINY26L-8SI Atmel, ATTINY26L-8SI Datasheet

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... Speed Grades – MHz for ATtiny26L – MHz for ATtiny26 • Power Consumption at 1 MHz, 3V and 25°C for ATtiny26L – Active 16 MHz, 5V and 25°C: Typ 15 mA – Active 1 MHz, 3V and 25°C: 0.70 mA – Idle Mode 1 MHz, 3V and 25°C: 0.18 mA – Power-down Mode: < 1 µA ® ...

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Pin Configuration Note: ATtiny26(L) 2 (MOSI/DI/SDA/OC1A) PB0 (MISO/DO/OC1A) PB1 (SCK/SCL/OC1B) PB2 (OC1B) PB3 VCC GND (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5 (ADC9/INT0/T0) PB6 (ADC10/RESET) PB7 MLF Top View NC 1 (OC1B) PB3 VCC 4 GND (ADC7/XTAL1) ...

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... Power-down mode. The device is manufactured using Atmel’s high density non-volatile memory technology. By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny26( powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications ...

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Block Diagram Figure 1. The ATtiny26(L) Block Diagram VCC GND AVCC ATtiny26(L) 4 8-BIT DATA BUS PROGRAM STACK COUNTER POINTER PROGRAM SRAM FLASH INSTRUCTION GENERAL REGISTER PURPOSE REGISTERS X INSTRUCTION Y DECODER Z CONTROL ALU LINES STATUS REGISTER PROGRAMMING ISP ...

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Pin Descriptions VCC Digital supply voltage pin. GND Digital ground pin. AVCC AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be externally connected to V through a low-pass filter. See page 94 ...

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... Information Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compi- lation ...

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AVR CPU Core Architectural The fast-access Register File concept contains 32 x 8-bit general purpose working registers with Overview a single clock cycle access time. This means that during one single clock cycle, one ALU (Arith- metic Logic Unit) operation ...

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The program memory is In- System programmable Flash memory. With the relative jump and relative call instructions, the whole address space is directly accessed. All AVR instructions have a single ...

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All of the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exceptions are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and ...

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Status Register – The AVR Status Register – SREG – at I/O space location $3F is defined as: SREG Bit $3F ($5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be ...

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Stack Pointer – SP The ATtiny26(L) Stack Pointer is implemented as an 8-bit register in the I/O space location $3D ($5D). As the ATtiny26(L) data memory has 224 ($E0) locations, eight bits are used. Bit $3D ($5D) Read/Write Initial Value ...

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Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 7. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word the destination ...

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Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word. Data Indirect Figure 10. Data Indirect Addressing Operand address is the contents of the X-, Y-, or ...

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The X-, Y-, or Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or Z-register prior to incrementing. Constant Addressing Figure 13. Code Memory Constant Addressing Using the LPM Instruction Constant byte address is ...

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Program execution continues at address The relative address k is from -2048 to 2047. 1477K–AVR–08/10 15 ...

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Memories The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crys- tal for the chip. No internal clock division is used. Figure 16 shows the parallel instruction fetches and instruction executions enabled by ...

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Figure 18. On-chip Data SRAM Access Cycles In-System The ATtiny26(L) contains 2K bytes On-chip In-System Programmable Flash memory for pro- Programmable gram storage. Since all instructions are 16- or 32-bit words, the Flash is organized 16. The ...

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The five different addressing modes for the data memory cover: Direct, Indirect with Displace- ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing ...

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EEPROM Data Bit Register – EEDR $1D ($3D) Read/Write Initial Value • Bit 7..0 – EEDR7..0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by ...

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The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor- rect address is set up in the EEAR Register, the EERE bit must be set. When the EERE bit is cleared (zero) ...

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Table 2. ATtiny26(L) I/O Space Address Hex $3A ($5A) $39 ($59) $38 ($58) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $29 ($29) $21 ($41) $1E ...

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SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chap- ter for more details. For compatibility with future ...

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System Clock and Clock Options Clock Systems Figure 20 presents the principal clock systems in the AVR and their distribution. All of the clocks and their need not be active at a given time. In order to reduce power consumption, ...

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Internal PLL for Fast The internal PLL in ATtiny26(L) generates a clock frequency that is 64x multiplied from nomi- Peripheral Clock nally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal ...

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Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below on Table 3. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.The ...

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Watchdog Oscillator is voltage dependent as shown in the Electrical Characteristics section. Table 5. Number of Watchdog Oscillator Cycles Typ Time-out (V Default Clock The deviced is shipped with CKSEL = “0001”, SUT = “10”, and PLLCK ...

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The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 7. Table 7. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 Notes: Low-frequency To use ...

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External RC For timing insensitive applications, the external RC configuration shown in Figure 23 can be Oscillator used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT ...

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... RC Oscillator. At 5V, 25°C and 1.0 MHz Oscillator frequency selected, this calibration gives a fre-quency within ± the nominal frequency. Using run-time calibra- tion methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 1% accuracy at any given V chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the reset time-out. For more information on the pre-programmed calibration value, see the section “ ...

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EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the oscillator is intended for calibration to 1.0, 2.0, ...

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High Frequency There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as PLL Clock – a system ...

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System Control The ATtiny26(L) provides four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset and Reset threshold (V • External Reset. To use the PB7/RESET pin as an External ...

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... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1 for ATtiny26L and BODLEVEL=0 for ATtiny26. BODLEVEL=1 is not applicable for ATtiny26. decreases below detection level. ...

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Figure 26. MCU Start-up, RESET Tied to VCC TIME-OUT INTERNAL Figure 27. MCU Start-up, RESET Controlled Externally TIME-OUT INTERNAL External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns ...

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Brown-out ATtiny26(L) has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD Detection is enabled (BODEN programmed), and V Reset is immediately activated. ...

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MCU Status Bit Register – MCUSR $34 ($54) Read/Write Initial Value • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This ...

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Power Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- Management tion to the application’s requirements. and Sleep To ...

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The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre- sponding interrupt mask is set (one). The activity on the external INT0 pin that activates the interrupt is defined in the following ...

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If the wake-up condition disappears before the MCU wakes up and starts to execute, e.g., a low level on INT0 is not held long enough, the interrupt causing the wake-up will not be executed. Standby Mode When the SM1..0 bits ...

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Minimizing Power There are several issues to consider when trying to minimize the power consumption in an AVR Consumption controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so ...

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I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the ...

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Figure 32. General Digital I/O Note: Configuring the Pin Each port pin consists of 3 Register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description for I/O Ports” on page 56, the DDxn bits are accessed at the DDRx ...

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Table 21 summarizes the control signals for the pin value. Table 21. Port Pin Configurations DDxn Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read ...

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Figure 34. Synchronization when Reading a Software Assigned Pin Value INSTRUCTIONS ATtiny26(L) 44 SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 0xFF nop in r17, PINx 0x00 0xFF t pd 1477K–AVR–08/10 ...

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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...

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Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs should ...

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Table 22 summarizes the function of the overriding signals. The pin and port indexes from Fig- ure 35 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 22. ...

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MCU Control Register The MCU Control Register contains control bits for general MCU functions. – MCUCR Bit $35 ($55) Read/Write Initial Value • Bit 6 – PUD: Pull-up Disable When this bit is set (one), the pull-ups in the I/O ...

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AIN0: Analog Comparator Positive input and ADC5: ADC input channel 5 as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator or analog to digital converter. PCINT1: ...

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Table 25. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Notes: ATtiny26(L) 50 PA3/AREF/PCINT1 ADMUX[REFS0] 0 ADMUX[REFS0 (1) PCINT1_ENABLE • (2) ~ ADMUX[REFS0] 1 PCINT1 ANALOG ...

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Alternate Functions Of Port B has an alternate functions for the ADC, Clocking, Timer/Counters, USI, SPI programming Port B and pin change interrupt. The ADC is described in “Analog to Digital Converter” on page 94, Clocking in “AVR CPU Core” ...

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The masking alternate function is the pin usage as RESET. Digital input is enabled on pin PB7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function. • ADC9/INT0/T0/PCINT1 – Port B, ...

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PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate function is the output compare ...

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DI/SDA/OC1A/PCINT0 – Port B, Bit 0 DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions., so pin must be configure as an input. SDA: Serial Data in USI Two-wire mode. Serial data ...

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Table 28. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PB3/OC1B/PCINT0 PUOE 0 PUOV 0 DDOE 0 DDOV 0 (1) PVOE OC1B_ENABLE PVOV OC1B DIEOE PCINT0_ENABLE ~OC1B_ENABLE DIEOV 1 DI PCINT0 AIO – Notes: 1. Enabling of the Timer/Counter1 ...

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Register Description for I/O Ports Port A Data Register – Bit PORTA $1B ($3B) Read/Write Initial Value Port A Data Direction Bit Register – DDRA $1A ($3A) Read/Write Initial Value Port A Input Pins Bit Address – PINA $19 ($39) ...

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Interrupts Interrupt Vectors The ATtiny26(L) provides eleven interrupt sources. These interrupts and the separate Reset Vector, each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) ...

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Interrupt Handling The ATtiny26(L) has two 8-bit Interrupt Mask Control Registers; GIMSK – General Interrupt Mask Register and TIMSK – Timer/Counter Interrupt Mask Register. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are ...

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Bit 5 – PCIE1: Pin Change Interrupt Enable1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the interrupt pin change is enabled on analog pins PB[7:4], PA[7:6] and PA[3]. ...

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Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 compare match A, interrupt is enabled. The corresponding interrupt at vector ...

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Bit 2 – TOV1: Timer/Counter1 Overflow Flag The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hard- ware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared, after synchronization clock ...

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External The External Interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt will trig- ger even if the INT0 pin is configured as an output. This feature provides a way of generating a Interrupt software interrupt. ...

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Table 30. Alternative Functions Pin PA3 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Notes: A fuse value of “0” is programmed, “1” is unprogrammed. 1477K–AVR–08/10 Control Register[Bit Name] which Alternate Function set the Alternate Function AREF ADMUX[REFS0] ...

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Timer/Counters The ATtiny26(L) provides two general purpose 8-bit Timer/Counters. The Timer/Counters have separate prescaling selection from the separate prescaler. The Timer/Counter0 clock (CK) as the clock timebase. The Timer/Counter1 has two clocking modes, a synchronous mode and an asynchronous mode. ...

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Timer/Counter1 Figure 37 shows the Timer/Counter1 prescaler. For Timer/Counter1 the clock selections are between PCK to PCK/16384 and stop in asynchronous mode and CK to CK/16384 and stop in Prescaler synchronous. The clock options are described in Table 34 on ...

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Figure 38. Timer/Counter0 Block Diagram Timer/Counter0 Bit Control Register – $33 ($53) TCCR0 Read/Write Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and always read as zero. • Bit 3 – ...

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The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used, the correspond- ing setup must be performed in the actual Data Direction ...

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Figure 39. Timer/Counter1 Synchronization Register Block Diagram PCKE CK PCK SYNC MODE ASYNC MODE Timer/Counter1 and the prescaler allow running the CPU from any clock source while the pres- caler is operating on the fast 64 MHz PCK clock in ...

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Figure 40. Timer/Counter1 Block Diagram Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt Flag Register – TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1A and TCCR1B. The interrupt enable/disable settings are found ...

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Timer/Counter1 Bit Control Register A – $30 ($50) TCCR1A Read/Write Initial Value • Bits 7, 6 – COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a ...

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The automatic action pro- grammed in COM1B1 and COM1B0 takes place compare match had occurred, but no interrupt is generated. The FOC1B bit always ...

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Bits 3..0 – CS13, CS12, CS11, CS10: Clock Select Bits and 0 The Clock Select bits and 0 define the prescaling source of Timer/Counter1. Table 34. Timer/Counter1 Prescale Select CS13 ...

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A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow- ing the compare event. Timer/Counter1 Bit Output Compare $2C ($4C) RegisterB – OCR1B Read/Write Initial Value The Output Compare Register 8-bit read/write ...

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When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable PCK for Timer/Counter1. After the PLL is enabled, it takes about 64 µs/100 µs (typical/worst case) for the PLL to ...

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Table 35. Compare Mode Select in PWM Mode COM1x1 Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data value is first transferred to a temporary location. The value is ...

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Table 36. PWM Outputs OCR1x = $00 or OCR1C COM1x1 PWM mode, the Timer Overflow Flag – TOV1, is set as in normal Timer/Counter mode. Timer Overflow Interrupt1 ...

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Table 37. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency (kHz) 1477K–AVR–08/10 Clock Selection CS13..CS10 20 PCK/16 30 PCK/16 40 PCK/8 50 PCK/8 60 PCK/8 70 PCK/4 80 PCK/4 90 PCK/4 100 PCK/4 110 PCK/4 120 PCK/4 130 ...

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Watchdog The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at V Timer controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted from 16 to 2048 ...

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The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watch- dog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in Table 38. Table 38. Watchdog Timer Prescale Select WDP2 0 ...

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Universal Serial The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly Interface – USI higher transfer rates and uses less code space than ...

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Register Descriptions USI Data Register – Bit USIDR $0F ($2F) Read/Write Initial Value The USI uses no buffering of the serial register, i.e., when accessing the Data Register (USIDR) the serial register is accessed directly serial clock occurs ...

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Bit 5 – USIPF: Stop Condition Flag When Two-wire mode is selected, the USIPF flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is ...

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Bit 5..4 – USIWM1..0: Wire Mode These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode ...

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Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data ...

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Functional Descriptions Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. ...

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The USI clock modes corresponds to the SPI data mode 0 and 1. Referring to the timing diagram (Figure 46.), a bus transfer involves the following steps: 1. The ...

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The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/2): SPITransfer_Fast: ret SPI Slave Operation The following code demonstrates how to use the USI module as a SPI slave: Example ...

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Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag is set. Two-wire ...

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Figure 48. Two-wire Mode, Typical Timing Diagram SDA SCL Referring to the timing diagram (Figure 48.), a bus transfer involves the following steps: 1. The a start condition is generated by the master by forcing the SDA low line while ...

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Start Condition The start condition detector is shown in Figure 49. The SDA line is delayed (in the range Detector 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled ...

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Analog The Analog Comparator compares the input values on the positive pin PA6 (AIN0) and negative pin PA7 (AIN1). When the voltage on the positive pin PA6 (AIN0) is higher than the voltage on Comparator the negative pin PA7 (AIN1), ...

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Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is ...

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Table 42. Analog Comparator Input Selection ACME Notes: 1477K–AVR–08/10 (3) ADEN MUX3...0 Analog Comparator Negative Input X XXXX AIN1 1 XXXX AIN1 ...

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Analog to Digital Converter Features • 10-bit Resolution • ±2 LSB Absolute Accuracy • 0.5 LSB Integral Non-linearity • Optional Offset Cancellation • 260 µs Conversion Time • 11 Multiplexed Single Ended Input Channels • 8 Differential Input ...

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Figure 51. Analog to Digital Converter Block Schematic VCC AREF GND ADC10 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approxi- mation. The ...

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This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. The ADC can operate in two modes – Single Conversion and ...

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The ADC module contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADPS bits in ADCSR are used to generate a proper ADC clock input frequency from any chip clock frequency above 100 kHz. ...

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Figure 54. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL Figure 55. ADC Timing Diagram, Free Running Conversion Table 43. ADC Conversion Time Condition Extended conversion Normal conversions Changing Channel The MUXn and REFS1:0 bits ...

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Special care should be taken when changing differential channels. Once a differential channel has been selected, the gain stage may take as much as 125 µs to stabilize to the new value. Thus conversions should not be started within the ...

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Figure 56. Differential Measurement Range Table 44. Correlation Between Input Voltage and Output Codes V ADCn V ADCm V + (1023/1024) V ADCm V + (1022/1024) V ADCm ... V + (1/1024) V ADCm V ADCm Example: ADMUX = 0xEB ...

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ADC Multiplexer Bit Selection Register – $07 ($27) ADMUX Read/Write Initial Value • Bit 7, 6 – REFS1, REFS0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 45. If these bits are ...

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Table 46. Input Channel and Gain Selections MUX4..0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 (1) 01101 01110 01111 10000 (1) 10001 10010 10011 10100 10101 (1) 10110 10111 11000 11001 11010 (1) 11011 ...

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ADC Control and Bit Status Register – $06 ($26) ADCSR Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned ...

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Bits 2..0 – ADPS2..0: ADC Prescaler Select Bits These bits determine the division factor between the CK frequency and the input clock to the ADC. Table 47. ADC Prescaler Selections ADPS2 ADC Data Register – ADCL and ADCH ADLAR ...

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Scanning Multiple Since change of analog channel always is delayed until a conversion is finished, the Free Run- ning mode can be used to scan multiple channels without interrupting the converter. Typically, Channels the ADC Conversion Complete interrupt will be ...

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Figure 57. ADC Power Connections ATtiny26(L) 106 (MOSI/DI/SDA/OC1A) PB0 1 (MISO/DO/OC1A) PB1 2 (SCK/SCL/OC1B) PB2 3 (OC1B) PB3 4 VCC 5 GND 6 (ADC7/XTAL1) PB4 7 8 (ADC8/XTAL2) PB5 (ADC9/INT0/T0) PB6 9 10 (ADC10/RESET) PB7 PA0 (ADC0 ...

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Memory Programming Program and Data The ATtiny26 provides two Lock bits which can be left unprogrammed (“1”) or can be pro- grammed (“0”) to obtain the additional features listed in Table 49. The Lock bits can only be Memory Lock ...

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Fuse Bits The ATtiny26 has two Fuse bytes. Table 50 and Table 51 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, ...

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... EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. ...

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Figure 58. Parallel Programming Table 54. Pin Name Mapping Signal Name in Programming Mode WR XA0 XA1/BS2 PAGEL/BS1 OE RDY/BSY DATA Note: Table 55. Pin Values used to Enter Programming Mode Pin PAGEL/BS1 XA1/BS2 XA0 WR ATtiny26(L) 110 WR PB0 ...

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Table 56. XA1 and XA0 Coding XA1 Note: Table 57. Command Byte Bit Coding Command Byte 1477K–AVR–08/10 (1) XA0 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by ...

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Parallel Programming Enter Programming The following algorithm puts the device in parallel programming mode: Mode Step 2-7 must be completed within 64ms. 1. Set Prog_enable pins listed in Table 55 on page 110, RESET and Vcc to 0V. 2. Apply ...

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Chip Erase The Chip Erase will erase the Flash and EEPROM not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. ...

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F. Load Address High byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “1”. This selects high address. 3. Set DATA = Address high byte ($00 - $03). 4. Give XTAL1 a positive pulse. ...

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Figure 60. Programming the Flash Waveforms PAGEL/BS1 RESET +12V Note: Programming the The EEPROM is organized in pages, see Table 53 on page 109. When programming the EEPROM EEPROM, the program data is latched into a page buffer. This allows ...

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Figure 61. Programming the EEPROM Waveforms RESET +12V Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 113 for details on Command and Address loading Load Command ...

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Programming the The algorithm for programming the Fuse high bits is as follows (refer to “Programming the Flash” Fuse High Bits on page 113 for details on Command and Data loading Load Command “0100 0000” Load ...

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Figure 63. Mapping Between BS1, BS2 and the Fuse- and Lock-bits During Read Reading the Signature The algorithm for reading the Signature bytes is as follows (refer to Programming the Flash for Bytes details on Command and Address loading): 1. ...

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Figure 65. Parallel Programming Timing, Loading Sequence with Timing Requirements PAGEL/BS1 Note: Figure 66. Parallel Programming Timing, Reading Sequence (Within the Same Page) with Tim- ing Requirements PAGEL/BS1 XA1/BS2 Note: 1477K–AVR–08/10 LOAD ADDRESS (LOW BYTE) t XLXH XTAL1 DATA ADDR0 ...

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Table 58. Parallel Programming Characteristics, V Symbol DVXH t XLXH t XHXL t XLDX t XLWL t WLBX t BVWL t WLWH t WLRL t WLRH t WLRH_CE t XLOL t BVDV t OLDV t ...

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Serial Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- Downloading put). After RESET is set ...

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SPI Serial When writing serial data to the ATtiny26, data is clocked on the rising edge of SCK. Programming When reading data from the ATtiny26, data is clocked on the falling edge of SCK. See Figure Algorithm 68, Figure 69, ...

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Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new page, the programmed value ...

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Table 61. Serial Programming Instruction Set Instruction Byte 1 Programming Enable 1010 1100 Chip Erase 1010 1100 Read Program Memory 0010 H000 Load Program Memory Page 0100 H000 Write Program Memory Page 0100 1100 Read EEPROM Memory 1010 0000 Write ...

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Serial Programming Figure 69. Serial Programming Timing Characteristics Table 62. Serial Programming Characteristics, T Otherwise Noted) Symbol 1/t CLCL t CLCL 1/t CLCL t CLCL t SHSL t SLSH t OVSH t SHOX t SLIV Note: 1477K–AVR–08/10 MOSI t OVSH ...

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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin except RESET with Respect to Ground ..............................-0. Voltage on RESET with Respect to Ground ....-0.5V to +13.0V Maximum ...

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... If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 6. Minimum V for Power-down is 2.5V. CC 1477K–AVR–08/10 Condition Min. Active 1 MHz (ATtiny26L) Active 4 MHz (ATtiny26L) Active 8 MHz (ATtiny26) Idle 1 MHz (ATtiny26L) Idle 4 MHz (ATtiny26L) Idle 8 MHz (ATtiny26) WDT enabled WDT disabled - ...

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External Clock Figure 70. External Clock Drive Waveforms Drive Waveforms External Clock Table 63. External Clock Drive Drive Symbol 1/t CLCL t CLCL t CHCX t CLCX t CLCH t CHCL Δ t CLCL Table 64. External RC Oscillator, Typical ...

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ADC Characteristics Table 65. ADC Characteristics, Single Ended Channels, T Symbol Parameter Resolution Absolute Accuracy (Including INL, DNL, Quantization Error, Gain and Offset Error) Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error Offset error Clock Frequency Conversion Time AVCC Analog ...

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Table 66. ADC Characteristics, Differential Channels, T Symbol Parameter Resolution Absolute Accuracy Integral Non-Linearity (INL) (Accuracy after Calibration for Offset and Gain Error) Gain Error Offset Error Clock Frequency Conversion Time AVCC Analog Supply Voltage V Reference Voltage REF V ...

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ATtiny26 The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and Typical with internal pull-ups enabled. A sine wave generator with rail-to-rail output ...

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Figure 72. Active Supply Current vs. Frequency ( MHz) Figure 73. Active Supply Current vs. V ATtiny26(L) 132 ACTIVE SUPPLY CURRENT vs. FREQUENCY MHz 2. ...

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Figure 74. Active Supply Current vs. V Figure 75. Active Supply Current vs. V 1477K–AVR–08/10 CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 MHz 2.5 3 3.5 CC ...

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Figure 76. Active Supply Current vs. V 1.8 1.6 1.4 1.2 0.8 0.6 0.4 0.2 Figure 77. Active Supply Current vs. V ATtiny26(L) 134 (Internal RC Oscillator, 1 MHz) CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz ...

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Figure 78. Active Supply Current vs. V Idle Supply Current Figure 79. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) 1477K–AVR–08/10 CC ACTIVE SUPPLY CURRENT vs. V 32kHz EXTERNAL OSCILLATOR 1.5 ...

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Figure 80. Idle Supply Current vs. Frequency ( MHz) Figure 81. Idle Supply Current vs. V ATtiny26(L) 136 IDLE SUPPLY CURRENT vs. FREQUENCY MHz 2. ...

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Figure 82. Idle Supply Current vs. V Figure 83. Idle Supply Current vs. V 1477K–AVR–08/10 (Internal RC Oscillator, 4 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 MHz 3.5 3 2.5 2 1 ...

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Figure 84. Idle Supply Current vs. V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Figure 85. Idle Supply Current vs. V ATtiny26(L) 138 (Internal RC Oscillator, 1 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz ...

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Figure 86. Idle Supply Current vs. V Power-down Supply Figure 87. Power-down Supply Current vs. V Current 1477K–AVR–08/10 (32 kHz External Oscillator) CC IDLE SUPPLY CURRENT vs. V 32kHz EXTERNAL OSCILLATOR 2.5 ...

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Figure 88. Power-down Supply Current vs. V Standby Supply Figure 89. Standby Supply Current vs. V Current ATtiny26(L) 140 POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 2.5 ...

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Figure 90. Standby Supply Current vs. V Figure 91. Standby Supply Current vs. V 1477K–AVR–08/10 CC STANDBY SUPPLY CURRENT vs MHz RESONATOR, WATCHDOG TIMER DISABLED 2 ...

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Figure 92. Standby Supply Current vs. V Figure 93. Standby Supply Current vs. V 120 100 ATtiny26(L) 142 CC STANDBY SUPPLY CURRENT vs MHz XTAL, WATCHDOG TIMER DISABLED ...

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Figure 94. Standby Supply Current vs. V Figure 95. Standby Supply Current vs. V 1477K–AVR–08/10 STANDBY SUPPLY CURRENT vs MHz XTAL, WATCHDOG TIMER DISABLED 120 100 2.5 3 3.5 STANDBY SUPPLY CURRENT ...

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Figure 96. Standby Supply Current vs. V 180 160 140 120 100 Pin Pull-up Figure 97. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 160 85 °C 140 120 100 ATtiny26(L) 144 CC STANDBY ...

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Figure 98. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 85 °C Figure 99. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V -40 °C 1477K–AVR–08/10 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 80 25 °C 70 -40 ...

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Figure 100. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V -40 °C Pin Driver Strength Figure 101. I/O Pin Source Current vs. Output Voltage (V ATtiny26(L) 146 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 60 ...

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Figure 102. I/O Pin Source Current vs. Output Voltage (V Figure 103. I/O Pin Sink Current vs. Output Voltage (V 1477K–AVR–08/10 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 30 -40 ° °C 85 °C 20 ...

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Figure 104. I/O Pin Sink Current vs. Output Voltage (V Figure 105. Reset Pin as I/O – Source Current vs. Output Voltage (V 1.4 1.2 0.8 0.6 0.4 0.2 ATtiny26(L) 148 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = ...

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Figure 106. Reset Pin as I/O – Source Current vs. Output Voltage (V Figure 107. Reset Pin as I/O –Sink Current vs. Output Voltage (V 1477K–AVR–08/10 RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE 2.5 -40 °C 2 ...

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Figure 108. Reset Pin as I/O – Sink Current vs. Output Voltage (V Pin Thresholds and Figure 109. I/O Pin Input Threshold Voltage vs. V Hysteresis ATtiny26(L) 150 RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = ...

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Figure 110. I/O Pin Input Threshold Voltage vs. V Figure 111. I/O Pin Input Hysteresis vs. V 1477K–AVR–08/10 I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 2 1 2.5 3 3.5 ...

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Figure 112. Reset Pin as I/O – Input Threshold Voltage vs Reset Pin Read as “1”) IH 2.5 1.5 0.5 Figure 113. Reset Pin as I/O – Input Threshold Voltage vs Reset Pin Read ...

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Figure 114. Reset Pin as I/O – Pin Hysteresis vs. V Figure 115. Reset Input Threshold Voltage vs. V 1477K–AVR–08/10 RESET PIN AS I/O - PIN HYSTERESIS vs. V 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3 ...

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Figure 116. Reset Input Threshold Voltage vs. V 2.5 1.5 0.5 Figure 117. Reset Input Pin Hysteresis vs. V 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 ATtiny26(L) 154 RESET INPUT THRESHOLD VOLTAGE vs. V VIL, RESET PIN ...

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BOD Thresholds and Figure 118. BOD Thresholds vs. Temperature (BOD Level is 4.0V) Analog Comparator Offset Figure 119. BOD Thresholds vs. Temperature (BOD Level is 2.7V) 1477K–AVR–08/10 BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.0V 4.3 4.2 4.1 4 3.9 3.8 ...

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Figure 120. Bandgap Voltage vs. V 1.236 1.234 1.232 1.23 1.228 1.226 1.224 1.222 1.22 1.218 1.216 Figure 121. Analog Comparator Offset Voltage vs. Common Mode Voltage (V 0.009 0.008 0.007 0.006 0.005 0.004 0.003 0.002 0.001 ATtiny26(L) 156 CC ...

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Figure 122. Analog Comparator Offset Voltage vs. Common Mode Voltage (V 0.009 0.008 0.007 0.006 0.005 0.004 0.003 0.002 0.001 Internal Oscillator Figure 123. Watchdog Oscillator Frequency vs. V Speed 1477K–AVR–08/10 ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0 ...

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Figure 124. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 8.9 8.4 7.9 7.4 6.9 6.4 Figure 125. Calibrated 8 MHz RC Oscillator Frequency vs. V 8.5 7.5 6.5 ATtiny26(L) 158 CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE -60 -40 ...

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Figure 126. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value Figure 127. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature 1477K–AVR–08/10 CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 17.5 15.5 13.5 11.5 9.5 7.5 5.5 3 ...

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Figure 128. Calibrated 4 MHz RC Oscillator Frequency vs. V 4.4 4.3 4.2 4.1 3.9 3.8 3.7 3.6 3.5 3.4 Figure 129. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value 9.6 8.6 7.6 6.6 5.6 4.6 3.6 2.6 1.6 ...

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Figure 130. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature Figure 131. Calibrated 2 MHz RC Oscillator Frequency vs. V 1477K–AVR–08/10 CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.15 2.1 2.05 2 1.95 1.9 1.85 1.8 1.75 -60 -40 -20 ...

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Figure 132. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0.8 Figure 133. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature 1.04 1.02 0.98 0.96 0.94 0.92 ATtiny26(L) 162 CALIBRATED 2MHz RC ...

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Figure 134. Calibrated 1 MHz RC Oscillator Frequency vs. V Figure 135. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value 1477K–AVR–08/10 CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. V 1.1 1.05 1 0.95 0.9 0.85 2 2.5 3 3.5 CALIBRATED ...

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Current Consumption Figure 136. Brown-out Detector Current vs Peripheral Units 0.035 0.03 0.025 0.02 0.015 0.01 0.005 Figure 137. ADC Current vs. V 250 200 150 100 ATtiny26(L) 164 BROWNOUT DETECTOR CURRENT vs. V -40 °C 25 °C ...

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Figure 138. AREF External Reference Current vs. V Figure 139. Analog Comparator Current vs. V 1477K–AVR–08/10 AREF EXTERNAL REFERENCE CURRENT vs. VCC 250 200 150 100 2.5 3 3.5 ANALOG COMPARATOR CURRENT vs. V 120 100 80 ...

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Figure 140. Programming Current vs. V Current Consumption Figure 141. Reset Supply Current vs Reset and Reset (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) Pulsewidth ATtiny26(L) 166 CC PROGRAMMING CURRENT vs. VCC ...

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Figure 142. Reset Supply Current vs MHz, Excluding Current Through The Reset Pull-up) Figure 143. Reset Pulsewidth vs. V 1200 1000 1477K–AVR–08/10 CC RESET SUPPLY CURRENT vs MHz, EXCLUDING CURRENT THROUGH THE ...

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Register Summary Address Name Bit 7 $3F ($5F) SREG I $3E ($5E) Reserved $3D ($5D) SP SP7 $3C ($5C) Reserved $3B ($5B) GIMSK - $3A ($5A) GIFR - $39 ($59) TIMSK - $38 ($58) TIFR - $37 ($57) Reserved $36 ...

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Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers ADIW Rdl, K Add Immediate to Word SUB Rd, Rr Subtract Two Registers SUBI Rd, K ...

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Instruction Set Summary (Continued) Mnemonic Operands Description LD Rd, Y Load Indirect LD Rd, Y+ Load Indirect and Post-inc. LD Rd, -Y Load Indirect and Pre-dec. LDD Rd,Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ ...

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... Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 1477K–AVR–08/10 Ordering Code (2) Package ATtiny26L-8PU 20P3 ATtiny26L-8SU 20S ATtiny26L-8SUR 20S ATtiny26L-8MU 32M1-A ATtiny26L-8MUR 32M1-A ATtiny26-16PU 20P3 ATtiny26-16SU 20S ATtiny26-16SUR 20S ATtiny26-16MU 32M1-A ATtiny26-16MUR 32M1-A Package Type ...

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Packaging Information 20P3 A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 ...

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20S 1477K–AVR–08/10 173 ...

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Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 R ...

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Errata The revision letter refers to the revision of the device. ATtiny26 Rev. • First Analog Comparator conversion may be delayed B/C/D 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, ...

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Datasheet Please note that the referring page numbers in this section refer to the complete document. Revision History Rev. 1477K-08/10 Added tape and reel part numbers in “Ordering Information” on page 171. Removed text “Not recommended for new design” from ...

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Updated DC Characteristics for V Characteristics” on page 126. 7. Updated V Fixed typo in “Absolute Accuracy” on page 130. 8. Added Figure 106 in “Pin Driver Strength” on page 146, Figure 120, Figure 121 and Figure 122 in ...

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ATtiny26(L) 178 1477K–AVR–08/10 ...

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Table of Features................................................................................................ 1 Contents Pin Configuration ................................................................................ 2 Description........................................................................................... 3 Block Diagram ...................................................................................................... 4 Pin Descriptions.................................................................................................... 5 General Information ............................................................................ 6 Resources ............................................................................................................ 6 Code Examples .................................................................................................... 6 AVR CPU Core ..................................................................................... 7 Architectural Overview.......................................................................................... 7 General Purpose Register ...

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Idle Mode ............................................................................................................ 38 ADC Noise Reduction Mode............................................................................... 38 Power-down Mode.............................................................................................. 38 Standby Mode .................................................................................................... 39 Minimizing Power Consumption ......................................................................... 40 I/O Ports.............................................................................................. 41 Introduction ......................................................................................................... 41 Ports as General Digital I/O ................................................................................ 41 Alternate Port Functions ..................................................................................... 46 Register ...

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Memory Programming .................................................................... 107 Program and Data Memory Lock Bits............................................................... 107 Fuse Bits........................................................................................................... 108 Signature Bytes ................................................................................................ 109 Calibration Byte ................................................................................................ 109 Page Size ......................................................................................................... 109 Parallel Programming Parameters, Pin Mapping, and Commands .................. 109 Parallel Programming ....................................................................................... 112 Serial ...

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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...