ATTINY26L-8SI Atmel, ATTINY26L-8SI Datasheet - Page 122

• Manufacturer Part Number: ATTINY26L-8SI
• Description: IC AVR MCU 2K LV 8MHZ IND 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY26L-8SI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SPI Serial
Programming
Algorithm
122
ATtiny26(L)
When writing serial data to the ATtiny26, data is clocked on the rising edge of SCK.
When reading data from the ATtiny26, data is clocked on the falling edge of SCK. See Figure
68, Figure 69, and Table 69 for timing details.
To program and verify the ATtiny26 in the serial programming mode, the following sequence is
recommended (See four byte instruction formats in Table 61):
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of synchro-
4. The Flash is programmed one page at a time. The page size is found in Table 52 on
5. The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the con-
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Apply power between V
tems, the programmer can not guarantee that SCK is held low during Power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
nization. When in synchronize the second byte ($53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all 4
bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
page 109. The memory page is loaded one byte at a time by supplying the 4 LSB of the
address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is
applied for given address. The Program Memory Page is stored by loading the Write Pro-
gram Memory Page instruction with the 6 MSB of the address. If polling is not used, the
user must wait at least t
the serial programming interface before the Flash write operation completes can result in
incorrect programming.
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling is not used, the user must wait
at least t
no $FFs in the data file(s) need to be programmed.
tent at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
CC
WD_EEPROM
power off.
before issuing the next byte. (See Table 60). In a chip erased device,
WD_FLASH
CC
and GND while RESET and SCK are set to “0”. In some sys-
before issuing the next page. (See Table 60). Accessing
1477K–AVR–08/10