ATMEGA64-16AI Atmel, ATMEGA64-16AI Datasheet - Page 160

• Manufacturer Part Number: ATMEGA64-16AI
• Description: IC AVR MCU 64K 16MHZ IND 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OCR2 – Output
Compare Register
TIMSK –
Timer/Counter
Interrupt Mask
Register
TIFR – Timer/Counter
Interrupt Flag Register
2490Q–AVR–06/10
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2 pin.
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match Interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter2 occurs, for example, when the OCF2 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow Interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, for example, when the TOV2 bit is set in the Timer/Counter
Interrupt Flag Register – TIFR.
• Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the
data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and
OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Inter-
rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
Bit
0x23 (0x43)
Read/Write
Initial Value
Bit
0x37 (0x57)
Read/Write
Initial Value
Bit
0x36 (0x56)
Read/Write
Initial Value
OCIE2
OCF2
R/W
R/W
R/W
7
0
7
0
7
0
TOIE2
TOV2
R/W
R/W
R/W
6
0
6
0
6
0
TICIE1
ICF1
R/W
R/W
R/W
5
0
5
0
5
0
OCIE1A
OCF1A
R/W
R/W
R/W
4
0
4
0
4
0
OCR2[7:0]
OCIE1B
OCF1B
R/W
R/W
R/W
3
0
3
0
3
0
TOV1
TOIE1
R/W
R/W
R/W
2
0
2
0
2
0
OCF0
OCIE0
R/W
R/W
R/W
1
0
1
0
1
0
ATmega64(L)
TOV0
TOIE0
R/W
R/W
R/W
0
0
0
0
0
0
OCR2
TIMSK
TIFR
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