ATMEGA64L-8MI Atmel, ATMEGA64L-8MI Datasheet - Page 155
ATMEGA64L-8MI
Manufacturer Part Number
ATMEGA64L-8MI
Description
IC AVR MCU 64K 8MHZ IND 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA64L-8MI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Timer/Counter
Timing Diagrams
2490Q–AVR–06/10
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the out-
put will be continuously low and if set equal to MAX the output will be continuously high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.
There are two cases that give a transition without a Compare Match.
•
•
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set.
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 68. Timer/Counter Timing Diagram, no Prescaling
Figure 69
OCR2 changes its value from MAX, like in
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
The timer starts counting from a higher value than the one in OCR2, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
TCNTn
(clk
TOVn
clk
clk
I/O
shows the same timing data, but with the prescaler enabled.
I/O
Tn
/1)
Figure 68
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
Figure 67
OCn has a transition from high to low even though there
MAX
Figure
67. When the OCR2 value is MAX the
BOTTOM
T2
ATmega64(L)
) is therefore shown as a
BOTTOM + 1
155
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