ATMEGA64L-8MI Atmel, ATMEGA64L-8MI Datasheet - Page 68
ATMEGA64L-8MI
Manufacturer Part Number
ATMEGA64L-8MI
Description
IC AVR MCU 64K 8MHZ IND 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA64L-8MI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Reading the Pin Value
2490Q–AVR–06/10
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be written to one to
disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 25
Table 25. Port Pin Configurations
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
tute a synchronizer. This is needed to avoid metastability if the physical pin changes value near
the edge of the internal clock, but it also introduces a delay.
the synchronization when reading an externally applied pin value. The maximum and minimum
propagation delays are denoted t
Figure 31. Synchronization when Reading an Externally Applied Pin Value
DDxn
0
0
0
1
1
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
summarizes the control signals for the pin value.
PORTxn
0
1
1
0
1
PINxn
r17
(in SFIOR)
PUD
X
0
1
X
X
Figure
XXX
Output
Output
pd,max
Input
Input
Input
I/O
30, the PINxn Register bit and the preceding latch consti-
and t
Pull-up
Yes
t
pd,min
No
No
No
No
pd, max
0x00
respectively.
XXX
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled
low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
t
pd, min
Figure 31
in r17, PINx
shows a timing diagram of
ATmega64(L)
0xFF
68
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