PIC18LF2439T-I/SO Microchip Technology, PIC18LF2439T-I/SO Datasheet - Page 170
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PIC18LF2439T-I/SO
Manufacturer Part Number
PIC18LF2439T-I/SO
Description
IC MCU FLASH 6KX16 EE A/D 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Specifications of PIC18LF2439T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (6K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
640 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
640 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18FXX39
17.1
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 17-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
Given the desired baud rate and F
integer value for the SPBRG register can be calculated
using the formula in Table 17-1. From this, the error in
baud rate can be determined.
EXAMPLE 17-1:
TABLE 17-1:
TABLE 17-2:
DS30485A-page 168
Legend: X = value in SPBRG (0 to 255)
TXSTA
RCSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
Desired Baud Rate
Solving for X:
Calculated Baud Rate
Error
Name
SYNC
0
1
USART Baud Rate Generator
(BRG)
X
X
X
Baud Rate Generator Register
CSRC
SPEN
Bit 7
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
(Asynchronous) Baud Rate = F
(Synchronous) Baud Rate = F
CALCULATING BAUD RATE ERROR
Bit 6
RX9
TX9
= F
= ( (F
= ((16000000 / 9600) / 64) – 1
=
=
=
=
=
=
[25.042] = 25
16000000 / (64 (25 + 1))
9615
(Calculated Baud Rate – Desired Baud Rate)
(9615 – 9600) / 9600
0.16%
OSC
BRGH = 0 (Low Speed)
OSC
SREN
TXEN
Bit 5
/ (64 (X + 1))
/ Desired Baud Rate) / 64 ) – 1
OSC
Desired Baud Rate
, the nearest
CREN
SYNC
Bit 4
ADDEN
Preliminary
Bit 3
OSC
OSC
—
/(64(X+1))
/(4(X+1))
BRGH
FERR
Bit 2
Example 17-1 shows the calculation of the baud rate
error for the following conditions:
• F
• Desired Baud Rate = 9600
• BRGH = 0
• SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the F
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
17.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
OSC
OERR
TRMT
Bit 1
= 16 MHz
SAMPLING
OSC
RX9D
TX9D
Bit 0
/(16(X + 1)) equation can reduce the
Baud Rate = F
BRGH = 1 (High Speed)
2002 Microchip Technology Inc.
0000 -010
0000 -00x
0000 0000
POR, BOR
Value on
N/A
OSC
/(16(X+1))
0000 -010
0000 -00x
0000 0000
All Other
Value on
RESETS
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