PIC18F8525-E/PT Microchip Technology, PIC18F8525-E/PT Datasheet - Page 154

• Manufacturer Part Number: PIC18F8525-E/PT
• Description: IC PIC MCU FLASH 24KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8525-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 2 x 8 bit
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6525/6621/8525/8621
16.3
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP4
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (CCP4M3:CCP4M0). At the same time, the
interrupt flag bit CCP4IF is set.
16.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
FIGURE 16-3:
DS39612B-page 152
I/O latch)
Note:
RG3/CCP4/P1D
Compare Mode
pin
CCP PIN CONFIGURATION
Clearing the CCP4CON register will force
the RG3/CCP4/P1D compare output latch
to the default low level. This is not the
PORTG I/O data latch.
Output Enable
TRISG<3>
COMPARE MODE OPERATION BLOCK DIAGRAM
Q
R
S
(ECCP1 and ECCP2 only)
Special Event Trigger
CCP4CON<3:0>
Mode Select
Output
Logic
Set Flag bit CCP4IF
Match
16.3.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
16.3.3
When the Generate Software Interrupt mode is chosen
(CCP4M3:CCP4M0 = 1010), the CCP4 pin is not
affected. Only a CCP interrupt is generated if enabled
and the CCP4IE bit is set.
16.3.4
Although shown in Figure 16-3, the compare on match
special event triggers are not implemented on CCP4 or
CCP5; they are only available on ECCP1 and ECCP2.
Their operation is discussed in detail in Section 17.2.1
“Special Event Trigger”.
TMR1H
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
T3CCP2
TMR1L
CCPR4H CCPR4L
Comparator
 2005 Microchip Technology Inc.
0
1
TMR3H
TMR3L