DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 88

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

Complementary mode by default upon a device Reset.
dsPIC30F2010
14.5.1
The four PWM duty cycle registers are double-buffered
to allow glitchless updates of the PWM outputs. For
each duty cycle, there is a duty cycle register that is
accessible by the user and a second duty cycle register
that holds the actual compare value used in the present
PWM period.
For edge-aligned PWM output, a new duty cycle value
will be updated whenever a match with the PTPER
register occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
duty cycle registers when the PWM time base is
disabled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
When the PWM time base is in the Up/Down Counting
mode, new duty cycle values are updated when the
value of the PTMR register is zero and the PWM time
base begins to count upwards. The contents of the duty
cycle buffers are automatically loaded into the duty
cycle registers when the PWM time base is disabled
(PTEN = 0).
When the PWM time base is in the Up/Down Counting
mode with double updates, new duty cycle values are
updated when the value of the PTMR register is zero,
and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the duty
cycle registers when the PWM time base is disabled
(PTEN = 0).
14.6
In the Complementary mode of operation, each pair of
PWM outputs is obtained by a complementary PWM
signal. A dead time may be optionally inserted during
device switching, when both outputs are inactive for a
short period (Refer to Section 14.7 “Dead-Time
Generators”).
In Complementary mode, the duty cycle comparison
units are assigned to the PWM outputs as follows:
• PDC1 register controls PWM1H/PWM1L outputs
• PDC2 register controls PWM2H/PWM2L outputs
• PDC3 register controls PWM3H/PWM3L outputs
The Complementary mode is selected for each PWM
I/O pin pair by clearing the appropriate PMODx bit in the
PWMCON1 SFR. The PWM I/O pins are set to
DS70118H-page 88
Complementary PWM Operation
DUTY CYCLE REGISTER BUFFERS
14.7
Dead-time generation may be provided when any of
the PWM I/O pin pairs are operating in the
Complementary Output mode. The PWM outputs use
Push-Pull drive circuits. Due to the inability of the
power output devices to switch instantaneously, some
amount of time must be provided between the turn off
event of one PWM output in a complementary pair and
the turn on event of the other transistor.
14.7.1
Each complementary output pair for the PWM module
has a 6-bit down counter that is used to produce the
dead-time insertion. As shown in Figure 14-4, the
dead-time unit has a rising and falling edge detector
connected to the duty cycle comparison output.
14.7.2
The amount of dead time provided by the dead-time
unit is selected by specifying the input clock prescaler
value and a 6-bit unsigned value.
Four input clock prescaler selections have been
provided to allow a suitable range of dead times, based
on the device operating frequency. The dead-time
clock
DTAPS<1:0> and DTBPS<1:0> control bits in the
DTCON1 SFR. One of four clock prescaler options
(T
dead-time value.
After the prescaler value is selected, the dead time is
adjusted by loading a 6-bit unsigned value into the
DTCON1 SFR.
The dead-time unit prescaler is cleared on the following
events:
• On a load of the down timer due to a duty cycle
• On a write to the DTCON1 register.
• On any device Reset.
CY
comparison edge event.
Note:
, 2 T
prescaler
Dead-Time Generators
CY
DEAD-TIME GENERATORS
DEAD-TIME RANGES
The user should not modify the DTCON1
values while the PWM module is operating
(PTEN = 1). Unexpected results may
occur.
, 4 T
CY
value
or 8 T
© 2008 Microchip Technology Inc.
is
CY
) is selected for the
selected
using
the