DSPIC30F6012T-20I/PF Microchip Technology, DSPIC30F6012T-20I/PF Datasheet - Page 219

• Manufacturer Part Number: DSPIC30F6012T-20I/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012T-20I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6012T20IP

I
I/O Pin Specifications
I/O Ports .............................................................................. 63
I
I
I
I
I
I
Idle Current (I
In-Circuit Serial Programming (ICSP) ......................... 51, 141
Input Capture (CAPX) Timing Characteristics .................. 192
Input Capture Module ......................................................... 83
Input Capture Operation During Sleep and Idle Modes ...... 84
Input Capture Timing Requirements ................................. 192
Input Change Notification Module ....................................... 67
Instruction Addressing Modes............................................. 39
 2004 Microchip Technology Inc.
2
2
2
2
2
2
C 10-bit Slave Mode Operation ........................................ 97
C 7-bit Slave Mode Operation .......................................... 97
C Master Mode Operation ................................................ 99
C Master Mode Support ................................................... 99
C Module .......................................................................... 95
S Mode Operation .......................................................... 131
Input .......................................................................... 179
Output ....................................................................... 180
Parallel (PIO) .............................................................. 63
Reception.................................................................... 98
Transmission............................................................... 97
Reception.................................................................... 97
Transmission............................................................... 97
Baud Rate Generator................................................ 100
Clock Arbitration........................................................ 100
Multi-Master Communication, Bus Collision and Bus Ar-
Reception.................................................................... 99
Transmission............................................................... 99
Addresses ................................................................... 97
Bus Data Timing Characteristics
Bus Data Timing Requirements
Bus Start/Stop Bits Timing Characteristics
General Call Address Support .................................... 99
Interrupts..................................................................... 98
IPMI Support ............................................................... 99
Operating Function Description .................................. 95
Operation During CPU Sleep and Idle Modes .......... 100
Pin Configuration ........................................................ 95
Programmer’s Model................................................... 95
Register Map............................................................. 101
Registers..................................................................... 95
Slope Control .............................................................. 99
Software Controlled Clock Stretching (STREN = 1).... 98
Various Modes ............................................................ 95
Data Justification....................................................... 131
Frame and Data Word Length Selection................... 131
Interrupts..................................................................... 84
Register Map............................................................... 85
CPU Idle Mode............................................................ 84
CPU Sleep Mode ........................................................ 84
Register Map for dsPIC30F6011/6012 (Bits 15-8)...... 67
Register Map for dsPIC30F6011/6012 (Bits 7-0)........ 67
Register Map for dsPIC30F6013/6014 (Bits 15-8)...... 67
Register Map for dsPIC30F6013/6014 (Bits 7-0)........ 67
File Register Instructions ............................................ 39
NVMCON ............................................................ 52
NVMKEY............................................................. 52
bitration ............................................................. 100
Master Mode ..................................................... 202
Slave Mode ....................................................... 204
Master Mode ..................................................... 203
Slave Mode ....................................................... 205
Master Mode ..................................................... 202
Slave Mode ....................................................... 204
IDLE
) ............................................................ 175
dsPIC30F6011/6012/6013/6014
Preliminary
Instruction Set
Interrupt Controller
Interrupt Priority .................................................................. 46
Interrupt Sequence ............................................................. 48
Interrupts ............................................................................ 45
L
Load Conditions................................................................ 183
Low Voltage Detect (LVD) ................................................ 152
Low-Voltage Detect Characteristics.................................. 180
LVDL Characteristics ........................................................ 181
M
Memory Organization ......................................................... 25
Modes of Operation
Modulo Addressing ............................................................. 40
MPLAB ASM30 Assembler, Linker, Librarian ................... 166
MPLAB ICD 2 In-Circuit Debugger ................................... 167
MPLAB ICE 2000 High-Performance Universal
MPLAB ICE 4000 High-Performance Universal
MPLAB Integrated Development Environment
MPLINK Object Linker/MPLIB Object Librarian ................ 166
N
NVM
O
OC/PWM Module Timing Characteristics ......................... 193
Operating Current (I
Oscillator
Oscillator Selection ........................................................... 141
Oscillator Start-up Timer
Fundamental Modes Supported ................................. 39
MAC Instructions ........................................................ 40
MCU Instructions ........................................................ 39
Move and Accumulator Instructions ........................... 40
Other Instructions ....................................................... 40
Overview................................................................... 160
Summary .................................................................. 157
Register Map .............................................................. 50
Interrupt Stack Frame................................................. 49
Core Register Map ..................................................... 35
Disable...................................................................... 113
Initialization............................................................... 113
Listen All Messages.................................................. 113
Listen Only................................................................ 113
Loopback .................................................................. 113
Normal Operation ..................................................... 113
Applicability................................................................. 42
Operation Example..................................................... 41
Start and End Address ............................................... 41
W Address Register Selection.................................... 41
In-Circuit Emulator.................................................... 167
In-Circuit Emulator.................................................... 167
Software ................................................................... 165
Register Map .............................................................. 55
Configurations .......................................................... 144
Operating Modes (Table).......................................... 142
System Overview...................................................... 141
Fail-Safe Clock Monitor .................................... 145
Fast RC (FRC).................................................. 145
Initial Clock Source Selection ........................... 144
Low Power RC (LPRC)..................................... 145
LP Oscillator Control......................................... 144
Phase Locked Loop (PLL) ................................ 145
Start-up Timer (OST)........................................ 144
DD
) .................................................... 173
DS70117E-page 217