AT90CAN128-16AJ Atmel, AT90CAN128-16AJ Datasheet - Page 100
![IC MCU AVR FLASH 128K 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT90CAN128-16AJ
Manufacturer Part Number
AT90CAN128-16AJ
Description
IC MCU AVR FLASH 128K 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16AJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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12.2.1
12.2.2
12.3
12.4
100
Timer/Counter Clock Sources
Counter Unit
AT90CAN32/64/128
Registers
Definitions
The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter-
rupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt
Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Reg-
ister (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the Waveform Generator to gener-
ate a PWM or variable frequency output on the Output Compare pin (OC0A).
Compare Unit” on page 101.
Flag (OCF0A) which can be used to generate an Output Compare interrupt request.
The following definitions are used extensively throughout the section:
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0A). For details on clock sources and pres-
caler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
12-2
Figure 12-2. Counter Unit Block Diagram
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surroundings.
“Timer/Counter3/1/0 Prescalers” on page
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is depen-
dent on the mode of operation.
DATA BUS
TCNTn
for details. The compare match event will also set the Compare
direction
count
clear
bottom
Control Logic
96.
top
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
7679H–CAN–08/08
See “Output
T0
).
Figure
Tn
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