ATMEGA48V-10MI Atmel, ATMEGA48V-10MI Datasheet - Page 134
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ATMEGA48V-10MI
Manufacturer Part Number
ATMEGA48V-10MI
Description
IC AVR MCU 4K 5V 12MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA48V-10MI
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA48V-12MI
ATMEGA48V-12MI
ATMEGA48V-12MI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48V-10MI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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15.11.7
15.11.8
134
ATmega48/88/168
ICR1H and ICR1L – Input Capture Register 1
TIMSK1 – Timer/Counter1 Interrupt Mask Register
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7, 6 – Res: Reserved Bits
These bits are unused bits in the ATmega48/88/168, and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 55) is executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 4, 3 – Res: Reserved Bits
These bits are unused bits in the ATmega48/88/168, and will always read as zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 55) is executed when the OCF1B Flag, located in
TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 55) is executed when the OCF1A Flag, located in
TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See
Bit
(0x87)
(0x86)
Read/Write
Initial Value
Bit
(0x6F)
Read/Write
Initial Value
“Interrupts” on page
See “Accessing 16-bit Registers” on page 109.
R/W
R
7
0
7
–
0
R/W
55) is executed when the TOV1 Flag, located in TIFR1, is set.
R
6
–
0
6
0
ICIE1
R/W
R/W
5
0
5
0
R/W
R
4
–
0
4
0
ICR1[15:8]
ICR1[7:0]
R/W
R
3
–
0
3
0
OCIE1B
R/W
R/W
2
0
2
0
OCIE1A
R/W
R/W
1
0
1
0
TOIE1
R/W
R/W
0
0
0
0
2545S–AVR–07/10
TIMSK1
ICR1H
ICR1L
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