ATMEGA8515L-8JJ Atmel, ATMEGA8515L-8JJ Datasheet - Page 136
![IC MCU AVR 8K 5V 8MHZ 44-PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATMEGA8515L-8JJ
Manufacturer Part Number
ATMEGA8515L-8JJ
Description
IC MCU AVR 8K 5V 8MHZ 44-PLCC
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8515L-8JJ
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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ATmega8515(L)
Figure 64. USART Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USART
(listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are
shared by all units. The clock generation logic consists of synchronization logic for exter-
nal clock input used by synchronous slave operation, and the baud rate generator. The
XCK (Transfer Clock) pin is only used by Synchronous Transfer mode. The Transmitter
consists of a single write buffer, a serial Shift Register, parity generator and control logic
for handling different serial frame formats. The write buffer allows a continuous transfer
of data without any delay between frames. The Receiver is the most complex part of the
USART module due to its clock and data recovery units. The recovery units are used for
asynchronous data reception. In addition to the recovery units, the Receiver includes a
Parity Checker, control logic, a Shift Register and a two level receive buffer (UDR). The
Receiver supports the same frame formats as the Transmitter, and can detect Frame
Error, Data OverRun and Parity Errors.
1. Refer to Figure 1 on page 2, Table 37 on page 73, and Table 31 on page 69 for
USART pin placement.
UCSRA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDR (Transmit)
UDR (Receive)
UBRR[H:L]
(1)
UCSRB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
PARITY
CLOCK
DATA
OSC
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
RX
TX
Receiver
UCSRC
2512K–AVR–01/10
XCK
RxD
TxD
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