ATMEGA8535L-8PJ Atmel, ATMEGA8535L-8PJ Datasheet - Page 150
![IC MCU AVR 8K 5V 8MHZ 40-DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA8535L-8PJ
Manufacturer Part Number
ATMEGA8535L-8PJ
Description
IC MCU AVR 8K 5V 8MHZ 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535L-8PJ
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Parity Bit Calculation
USART Initialization
150
ATmega8535(L)
The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in
UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that
changing the setting of any of these bits will corrupt all ongoing communication for both
the Receiver and Transmitter.
The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.
The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selec-
tion between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The
Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be
detected in the cases where the first stop bit is zero.
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is
used, the result of the exclusive or is inverted. The relation between the parity bit and
data bits is as follows::
If used, the parity bit is located between the last data bit and first stop bit of a serial
frame.
The USART has to be initialized before any communication can take place. The initial-
ization process normally consists of setting the baud rate, setting frame format and
enabling the Transmitter or the Receiver depending on the usage. For interrupt driven
USART operation, the Global Interrupt Flag should be cleared (and interrupts globally
disabled) when doing the initialization.
Before doing a re-initialization with a changed baud rate or frame format, be sure that
there are no ongoing transmissions during the period the registers are changed. The
TXC Flag can be used to check that the Transmitter has completed all transfers and the
RXC Flag can be used to check that there are no unread data in the receive buffer. Note
that the TXC Flag must be cleared before each transmission (before UDR is written) if it
is used for this purpose.
Sp
IDLE
P
P
d
n
even
odd
Stop bit, always high.
No transfers on the communication line (RxD or TxD). An IDLE line must be
high.
Parity bit using even parity
Parity bit using odd parity
Data bit n of the character
P
P
even
odd
=
=
d
d
n 1
n 1
–
–
⊕
⊕
…
…
⊕
⊕
d
d
3
3
⊕
⊕
d
d
2
2
⊕
⊕
d
d
1
1
⊕
⊕
d
d
0
0
⊕
⊕
0
1
2502K–AVR–10/06
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