ATMEGA8535L-8PJ Atmel, ATMEGA8535L-8PJ Datasheet - Page 88
![IC MCU AVR 8K 5V 8MHZ 40-DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA8535L-8PJ
Manufacturer Part Number
ATMEGA8535L-8PJ
Description
IC MCU AVR 8K 5V 8MHZ 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535L-8PJ
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Special Function IO Register –
SFIOR
88
ATmega8535(L)
Each half period of the external clock applied must be longer than one system clock
cycle to ensure correct sampling. The external clock must be guaranteed to have less
than half the system clock frequency (f
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-
ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than f
An external clock source can not be prescaled.
Figure 39. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be
reset. The bit will be cleared by hardware after the operation is performed. Writing a
zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share
the same prescaler and a reset of this prescaler will affect both timers. This bit will
always be read as zero.
Bit
Read/Write
Initial Value
PSR10
clk
T0
T1
I/O
1. The synchronization logic on the input pins (
Synchronization
Synchronization
ADTS2
R/W
7
0
ADTS1
R/W
6
0
ADTS0
R/W
5
0
clk_I/O
clk
Clear
T1
ExtClk
/2.5.
R
4
–
0
< f
clk_I/O
ACME
R/W
3
0
T1/T0)
/2) given a 50/50% duty cycle. Since
PUD
R/W
is shown in Figure 38.
2
0
(1)
PSR2
R/W
1
0
clk
PSR10
T0
R/W
2502K–AVR–10/06
0
0
SFIOR
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