ATTINY13-20SSJ Atmel, ATTINY13-20SSJ Datasheet - Page 41
![IC MCU AVR 1K 5V 20MHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY13-20SSJ
Manufacturer Part Number
ATTINY13-20SSJ
Description
IC MCU AVR 1K 5V 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY13-20SSJ
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Other names
ATTINY13-24SSJ
ATTINY13-24SSJ
ATTINY13-24SSJ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY13-20SSJ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 41 of 176
- Download datasheet (3Mb)
8.4
8.4.1
8.4.2
2535J–AVR–08/10
Register Description
MCUSR – MCU Status Register
WDTCR – Watchdog Timer Control Register
The MCU Status Register provides information on which reset source caused an MCU Reset.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset
the MCUSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.
• Bit 7 - WDTIF: Watchdog Timer Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDTIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDTIF is cleared by writing a logic one to the flag. When the I-bit
in SREG and WDTIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 - WDTIE: Watchdog Timer Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is
enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt
Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDTIF. Executing the corresponding interrupt vector will clear
WDTIE and WDTIF automatically by hardware (the Watchdog goes to System Reset Mode).
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
WDTIF
R/W
7
0
R
7
–
0
WDTIE
R/W
6
0
R
6
–
0
WDP3
R/W
5
0
R
5
–
0
WDCE
R/W
4
0
R
4
–
0
WDE
R/W
WDRF
R/W
3
X
3
WDP2
R/W
See Bit Description
BORF
2
0
R/W
2
WDP1
R/W
EXTRF
1
0
R/W
1
WDP0
R/W
PORF
0
0
R/W
0
WDTCR
MCUSR
41
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