ATTINY13-20SSJ Atmel, ATTINY13-20SSJ Datasheet - Page 63
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ATTINY13-20SSJ
Manufacturer Part Number
ATTINY13-20SSJ
Description
IC MCU AVR 1K 5V 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY13-20SSJ
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Other names
ATTINY13-24SSJ
ATTINY13-24SSJ
ATTINY13-24SSJ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY13-20SSJ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
11.6.1
11.7
11.7.1
11.7.2
2535J–AVR–08/10
Modes of Operation
Compare Output Mode and Waveform Generation
Normal Mode
Clear Timer on Compare Match (CTC) Mode
The design of the Output Compare pin logic allows initialization of the OC0x state before the out-
put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of
operation.
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.
For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the
OC0x Register is to be performed on the next Compare Match. For compare output actions in
the non-PWM modes refer to
page
A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0x strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output
mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare
Match
For detailed timing information refer to
11-10 on page 68
67.
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same
timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using the Out-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the Compare Match output frequency. It
also simplifies the operation of counting external events.
70, and for phase correct PWM refer to
(See “Compare Match Output Unit” on page
See “Register Description” on page 69.
and
Figure 11-11 on page 69
Table 11-2 on page
Figure 11-8 on page
Table 11-4 on page
69. For fast PWM mode, refer to
in
62.).
“Timer/Counter Timing Diagrams” on page
68,
Figure 11-9 on page
70.
Table 11-3 on
68,
Figure
63