TS87C58X2-VCA Atmel, TS87C58X2-VCA Datasheet - Page 19
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TS87C58X2-VCA
Manufacturer Part Number
TS87C58X2-VCA
Description
IC MCU 8BIT 32K OTP 40MHZ 40-DIP
Manufacturer
Atmel
Series
87Cr
Datasheet
1.TS87C54X2-LIC.pdf
(62 pages)
Specifications of TS87C58X2-VCA
Core Processor
8051
Core Size
8-Bit
Speed
40/30MHz
Connectivity
UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
9. TS80C54/58X2 Serial I/O Port
9.1
4431E–8051–04/06
Framing Error Detection
SMOD0=X
The serial I/O port in the TS80C54/58X2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as an Uni-
versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2
and 3). Asynchronous transmission and reception can occur simultaneously and at different
baud rates
Serial I/O port includes the following enhancements:
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1).
Figure 9-1.
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
9-3.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 9-
2. and Figure 9-3.).
Figure 9-2.
SMOD0=1
• Framing error detection
• Automatic address recognition
SM0/FE
SMOD1
RXD
FE
RI
SMOD0
SM1
Framing Error Block Diagram
UART Timings in Mode 1
Start
bit
SM2
-
D0
REN
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD = 0)
POF
To UART framing error control
D1
TB8
GF1
D2
RB8
GF0
D3
Data byte
D4
PD
TI
D5
IDL
RI
D6
SCON (98h)
PCON (87h)
D7
Stop
bit
AT/TS8xC54/8X2
19