TS87C54X2-VIE Atmel, TS87C54X2-VIE Datasheet - Page 25
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TS87C54X2-VIE
Manufacturer Part Number
TS87C54X2-VIE
Description
IC MCU 8BIT 16K OTP 40MHZ 44VQFP
Manufacturer
Atmel
Series
87Cr
Datasheet
1.TS87C54X2-LIC.pdf
(62 pages)
Specifications of TS87C54X2-VIE
Core Processor
8051
Core Size
8-Bit
Speed
40/30MHz
Connectivity
UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
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10. Interrupt System
4431E–8051–04/06
INT0
INT1
EXF2
TF0
TF1
TF2
RI
TI
Individual Enable
The TS80C54/58X2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown
in Figure 10-1.
Figure 10-1. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register (See Table 10-2.). This register also contains a global disable bit,
which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by
setting or clearing a bit in the Interrupt Priority register (See Table 10-3.) and in the Interrupt Pri-
ority High register (See Table 10-4.). shows the bit values and priority levels associated with
each combination.
Table 10-1.
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-
ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
IE0
IE1
IPH.x
Priority Level Bit Values
0
0
1
1
IPH, IP
3
0
3
0
3
0
3
0
3
0
3
0
Global Disable
IP.x
0
1
0
1
High priority
interrupt
Interrupt
polling
sequence, decreasing from
high to low priority
AT/TS8xC54/8X2
Low priority
interrupt
Interrupt Level Priority
3 (Highest)
0 (Lowest)
1
2
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