TS87C58X2-MIB Atmel, TS87C58X2-MIB Datasheet - Page 20
![IC MCU 8BIT 32K OTP 40MHZ 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
TS87C58X2-MIB
Manufacturer Part Number
TS87C58X2-MIB
Description
IC MCU 8BIT 32K OTP 40MHZ 44PLCC
Manufacturer
Atmel
Series
87Cr
Datasheet
1.TS87C54X2-LIC.pdf
(62 pages)
Specifications of TS87C58X2-MIB
Core Processor
8051
Core Size
8-Bit
Speed
40/20MHz
Connectivity
UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
9.1.1
9.1.2
20
AT/TS8xC54/8X2
Automatic Address Recognition
Given Address
Figure 9-3.
The automatic address recognition feature is enabled when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor commu-
nication feature by allowing the serial port to examine the address of each incoming command
frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON
register to generate an interrupt. This ensures that the CPU is not interrupted by command
frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configu-
ration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received
command frame address matches the device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broad-
cast address.
NOTE: The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Each device has an individual address that is specified in SADDR register; the SADEN register
is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given
address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The
following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SMOD0=0
SMOD0=1
SMOD0=1
RXD
FE
RI
RI
SADDR
SADEN
Given
UART Timings in Modes 2 and 3
Start
bit
D0
0101 0110b
1111 1100b
0101 01XXb
D1
D2
D3
Data byte
D4
D5
D6
D7
Ninth
D8
bit
Stop
bit
4431E–8051–04/06