DSPIC30F5016-20I/PT Microchip Technology, DSPIC30F5016-20I/PT Datasheet - Page 14
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DSPIC30F5016-20I/PT
Manufacturer Part Number
DSPIC30F5016-20I/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F5011T-20IPT.pdf
(34 pages)
3.DSPIC30F6010T-20IPF.pdf
(6 pages)
4.DSPIC30F5016-20IPT.pdf
(100 pages)
Specifications of DSPIC30F5016-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
DSPIC30F501620IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F Family Reference Manual
22. Page 7-23, Section 7.17.3 Clock
23. Page 7-24, Section 7.17.7.2 Aborting a
24. Page 10-4, Section 10.3.6 Wake-up from
25. Page 10-4, Section 10.4 IDLE Mode
DS80169E-page 14
On page 7-23, Section 7.17.3 Clock Switching
Tips, add the following note to the end:
Switching Tips
Clock Switch
On page 7-24, Section 7.17.7.2 Aborting a Clock
Switch, should be replaced with the following:
7.17.7.2
The following code sequence would be used to ABORT an unsuccessful clock switch:
MOV
MOV.B
MOV.B
MOV.B
MOV.B
BCLR
SLEEP on Interrupt
On page 10-4, Section 10.3.6 Wake-up from
SLEEP on Interrupt, the following text should be
added:
User interrupt sources that are assigned to CPU
priority level 0 cannot wake the CPU from SLEEP
mode, because the interrupt source is effectively
disabled. To use an interrupt as a wake-up
source, the CPU priority level for the interrupt
must be assigned to CPU priority level 1 or
greater.
On page 10-4, Section 10.4 IDLE Mode, the
following text should be added:
User interrupt sources that are assigned to CPU
priority level 0 cannot wake the CPU from IDLE
mode, because the interrupt source is effectively
disabled. To use an interrupt as a wake-up
source, the CPU priority level for the interrupt
must be assigned to CPU priority level 1 or
greater.
#OSCCON,W1
#0x46,W2
#0x57,W3
W2, [W1]
W3, [W1]
OSCCON,#OSWEN
Aborting a Clock Switch
Note:
The application should not attempt to switch to a clock of frequency lower than
100 KHz when the fail-safe clock monitor is enabled. If such clock switching is
performed, the device may generate an oscillator fail trap and switch to the Fast RC
oscillator.
; pointer to OSCCON
; first unlock code
; second unlock code
; write first unlock code
; write second unlock code
; ABORT the switch
2004 Microchip Technology Inc.