DSPIC30F5016-20I/PT Microchip Technology, DSPIC30F5016-20I/PT Datasheet - Page 6
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DSPIC30F5016-20I/PT
Manufacturer Part Number
DSPIC30F5016-20I/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F5011T-20IPT.pdf
(34 pages)
3.DSPIC30F6010T-20IPF.pdf
(6 pages)
4.DSPIC30F5016-20IPT.pdf
(100 pages)
Specifications of DSPIC30F5016-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
DSPIC30F501620IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F Family Reference Manual
10. Page 5-6, Section 5.3.2 NVMADR
DS80169E-page 6
On page 5-6, Section 5.3.2 NVMADR Register
should be replaced with the following:
Register
5.3.2 NVM Address Registers
There are two NVM Address Registers - NVMADRU and NVMADR. These two registers when
concatenated form the 24-bit effective address (EA) of the selected row or word for programming
operations. The NVMADRU register is used to hold the upper 8 bits of the EA, while the
NVMADR register is used to hold the lower 16 bits of the EA.
The register pair, NVMADRU:NVMADR, capture the EA<23:0> of the last table-write instruction
that has been executed and select the row of Flash or EEPROM memory to write/erase.
Figure 5-2 shows how the program memory EA is formed for programming and erase operations.
Although the NVMADRU and NVMADR registers are automatically loaded by the table-write
instructions, the user can also directly modify their contents before the programming operation
begins. A write to these registers will be required prior to an erase operation, because no table-
write instructions are required for any erase operation.
Figure 5-2: NVM Addressing with TBLPAG and NVM Address Registers
TBLPAG<7>
selects User
or Configuration
Space
Using
NVMADR
Addressing
NVMADRU Register
TBLPAG Reg
8 bits
24-bit PM address
NVMADR Register
NVMADR register loaded with contents of W
register EA used during last table-write instruction.
NVMADRU register loaded with contents of
TBLPAG register during last table-write instruction
W Register EA
16 bits
2004 Microchip Technology Inc.
EA<0> is
Byte Select