ATMEGA88V-10PU Atmel, ATMEGA88V-10PU Datasheet - Page 174
![IC AVR MCU 8K 10MHZ 1.8V 28DIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATMEGA88V-10PU
Manufacturer Part Number
ATMEGA88V-10PU
Description
IC AVR MCU 8K 10MHZ 1.8V 28DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATAVRTS2080B.pdf
(378 pages)
2.ATMEGA48-20AU.pdf
(35 pages)
3.ATMEGA88V-10PU.pdf
(377 pages)
Specifications of ATMEGA88V-10PU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART, Serial
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3 bit
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
10MHz
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA88V-10PU
Manufacturer:
AT
Quantity:
20 000
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- Download datasheet (8Mb)
19.3.3
19.3.4
19.4
174
Frame Formats
ATmega48/88/168
External Clock
Synchronous Clock Operation
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCKn pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency
is limited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxDn) is sampled at the
opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 19-3. Synchronous Mode XCKn Timing.
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is
used for data change. As
rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed
at falling XCKn edge and sampled at rising XCKn edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
UCPOL = 1
UCPOL = 0
osc
depends on the stability of the system clock source. It is therefore recommended to
Figure 19-2
RxD / TxD
RxD / TxD
XCK
XCK
Figure 19-3
for details.
shows, when UCPOLn is zero the data will be changed at
f
XCK
<
f
---------- -
OSC
4
Sample
Sample
2545S–AVR–07/10
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