ATMEGA88V-10PU Atmel, ATMEGA88V-10PU Datasheet - Page 199
![IC AVR MCU 8K 10MHZ 1.8V 28DIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATMEGA88V-10PU
Manufacturer Part Number
ATMEGA88V-10PU
Description
IC AVR MCU 8K 10MHZ 1.8V 28DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATAVRTS2080B.pdf
(378 pages)
2.ATMEGA48-20AU.pdf
(35 pages)
3.ATMEGA88V-10PU.pdf
(377 pages)
Specifications of ATMEGA88V-10PU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART, Serial
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3 bit
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
10MHz
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA88V-10PU
Manufacturer:
AT
Quantity:
20 000
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20.4
2545S–AVR–07/10
SPI Data Modes and Timing
Table 20-1.
Note:
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
ality is summarized in
all ongoing communication for both the Receiver and Transmitter.
Table 20-2.
Operating Mode
Synchronous Master
mode
UCPOLn
BAUD
f
UBRRn
OSC
0
0
1
1
1. The baud rate is defined to be the transfer rate in bit per second (bps)
Figure
Equations for Calculating Baud Rate Register Setting
UCPOLn and UCPHAn Functionality-
20-1. Data bits are shifted out and latched in on opposite edges of the XCKn
UCPHAn
Table
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
0
1
0
1
Equation for Calculating Baud
20-2. Note that changing the setting of any of these bits will corrupt
BAUD
SPI Mode
=
0
1
2
3
Rate
-------------------------------------- -
2 UBRRn
(
(1)
f
OSC
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
+
1
)
ATmega48/88/168
Equation for Calculating UBRRn
UBRRn
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
Value
=
------------------- - 1
2BAUD
f
OSC
–
199
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