AT89C51AC3-RLTIM Atmel, AT89C51AC3-RLTIM Datasheet - Page 85
AT89C51AC3-RLTIM
Manufacturer Part Number
AT89C51AC3-RLTIM
Description
IC 8051 MCU FLASH 64K 44VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51AC3-RLTUM.pdf
(140 pages)
Specifications of AT89C51AC3-RLTIM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Functional Description
Figure 44. SPI Module Block Diagram
Operating Modes
4383D–8051–02/08
SPSCR
SPCON
SPIF
SPR2
SPEN
-
OVR
SSDIS
SPI
Control
MODF
MSTR
Figure 44 shows a detailed structure of the SPI Module.
The Serial Peripheral Interface can be configured in one of the two modes: Master mode
or Slave mode. The configuration and initialization of the SPI Module is made through
two registers:
•
•
Once the SPI is configured, the data exchange is made using:
•
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-
pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
Internal Bus
The Serial Peripheral Control register (SPCON)
The Serial Peripheral Status and Control Register (SPSCR)
The Serial Peripheral DATa register (SPDAT)
SPTE
CPOL CPHA
UARTM SPTEIE MODFIE
SPR1
SPR0
SPDAT
Transmit Data Register
Receive Data Register
PERIPH
FCLK
7
Clock
Logic
Shift Register
6
5
4
3
SPI Interrupt
Request
2
1
0
M
S
Pin
Control
Logic
8-bit bus
1-bit signal
MOSI
MISO
SCK
SS
85
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