AT89C51AC3-RLTIM Atmel, AT89C51AC3-RLTIM Datasheet - Page 88
AT89C51AC3-RLTIM
Manufacturer Part Number
AT89C51AC3-RLTIM
Description
IC 8051 MCU FLASH 64K 44VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51AC3-RLTUM.pdf
(140 pages)
Specifications of AT89C51AC3-RLTIM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Manufacturer
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Figure 49. Queuing Transmission In Master Mode
88
MOSI
MISO
Data
SPTE
SCK
AT89C51AC3
MSB
MSB
Byte 1
B6
B6
BYTE 1 under transmission
B5
B5
B4
B4
When a transmission is in progress a new data can be queued and sent as soon as
transmission has been completed. So it is possible to transmit bytes without latency,
useful in some applications.
The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that
the user application can write SPDAT with the data to be transmitted until the SPTE
becomes cleared.
Figure 49 shows a queuing transmission in master mode. Once the Byte 1 is ready, it is
immediately sent on the bus. Meanwhile an other byte is prepared (and the SPTE is
cleared), it will be sent at the end of the current transmission. The next data must be
ready before the end of the current transmission.
In slave mode it is almost the same except it is the external master that start the
transmission.
Also, in slave mode, if no new data is ready, the last value received will be the next data
byte transmitted.
B3
B3
B2
B2
B1
B1
Byte 2
LSB
LSB MSB
MSB
B6
B6
BYTE 2 under transmission
B5
B5
B4
B4
B3
B3
Byte 3
B2
B2
B1
B1
LSB
LSB
4383D–8051–02/08
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