DSPIC30F3010T-20I/SO Microchip Technology, DSPIC30F3010T-20I/SO Datasheet - Page 127

• Manufacturer Part Number: DSPIC30F3010T-20I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010T-20I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.7
The analog input model of the 10-bit A/D converter is
shown in Figure 19-2. The total sampling time for the
A/D is a function of the internal amplifier settling time,
device V
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the voltage level on the analog input
pin. The source impedance (R
impedance (R
(R
required to charge the capacitor C
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the A/D
converter, the maximum recommended source imped-
ance, R
selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
FIGURE 19-2:
© 2005 Microchip Technology Inc.
SS
) impedance combine to directly affect the time
Note:
S
DD
A/D Acquisition Requirements
, is 5 k . After the analog input channel is
and the holding capacitor charge time.
IC
C
) and the internal sampling switch
PIN
Legend: C
VA
value depends on device package and is not tested. Effect of C
Rs
A/D CONVERTER ANALOG INPUT MODEL
V
I leakage
R
R
C
ANx
T
PIN
IC
SS
HOLD
C
PIN
HOLD
S
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
), the interconnect
various junctions
) must be allowed
. The combined
V
DD
V
V
T
T
= 0.6V
= 0.6V
Preliminary
R
I leakage
IC
500 nA
250
The user must allow at least 1 T
time, T
sample to be acquired. This sample time may be
controlled manually in software by setting/clearing the
SAMP bit, or it may be automatically controlled by the
A/D converter. In an automatic configuration, the user
must allow enough time between conversion triggers
so that the minimum sample time can be satisfied.
Refer
Characteristics"
requirements.
dsPIC30F3010/3011
SAMP
Sampling
Switch
to
R
SS
, between conversions to allow each
PIN
negligible if Rs
the
R
SS
V
for
SS
C
= DAC capacitance
= 4.4 pF
HOLD
3 k
Section 23.0
T
AD
5 k .
AD
and
DS70141B-page 125
period of sampling
sample
"Electrical
time