DSPIC30F3010T-20I/SO Microchip Technology, DSPIC30F3010T-20I/SO Datasheet - Page 83

• Manufacturer Part Number: DSPIC30F3010T-20I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010T-20I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.0
This section describes the Output Compare module
and associated operational modes. The features
provided by this module are useful in applications
requiring operational modes such as:
• Generation of Variable Width Output Pulses
• Power Factor Correction
Figure 13-1 depicts a block diagram of the Output
Compare module.
FIGURE 13-1:
© 2005 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046).
From GP Timer Module
Note:
OUTPUT COMPARE MODULE
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
TMR2<15:0
OUTPUT COMPARE MODE BLOCK DIAGRAM
0
Comparator
OCxRS
OCxR
TMR3<15:0>
1
OCTSEL
T2P2_MATCH
Preliminary
0
The key operational features of the Output Compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare during Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
These operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where x =
1,2,3,...,N). The dsPIC30F3010/3011 devices have 4/2
compare channels, respectively.
OCxRS and OCxR in the figure represent the dual
compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
T3P3_MATCH
dsPIC30F3010/3011
Mode Select
OCM<2:0>
1
Output
Logic
3
Set Flag bit
OCxIF
R
S
Q
Output Enable
(for x = 1, 2, 3 or 4)
DS70141B-page 81
OCx
OCFA