PIC16F716-I/ML Microchip Technology, PIC16F716-I/ML Datasheet - Page 12
![IC PIC MCU FLASH 2KX14 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F716-I/ML
Manufacturer Part Number
PIC16F716-I/ML
Description
IC PIC MCU FLASH 2KX14 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F716-ISO.pdf
(136 pages)
4.PIC16F716-ISO.pdf
(12 pages)
Specifications of PIC16F716-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F716-ISO PDF datasheet #3
- PIC16F716-ISO PDF datasheet #4
- Current page: 12 of 136
- Download datasheet (3Mb)
PIC16F716
TABLE 2-2:
DS41206B-page 10
80h
81h
82h
83h
84h
85h
86h
87h-89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh-91h
92h
93h-9Eh
9Fh
Legend:
Note
Address
1:
2:
3:
4:
5:
6:
7:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
PR2
ADCON1
These registers can be addressed from either bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are
transferred to the upper byte of the program counter.
Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.
The IRP and RP1 bits are reserved. Always maintain these bits clear.
On any device Reset, these pins are configured as inputs.
This is the value that will be in the PORT output latch.
Reserved bits, do not use.
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, Shaded locations are unimplemented,
read as ‘0’.
Name
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1,2)
SPECIAL FUNCTION REGISTER SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
TRISB7
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Unimplemented
RBPU
IRP
Bit 7
GIE
—
—
—
—
—
(4)
INTEDG
TRISB6
RP1
PEIE
ADIE
Bit 6
—
—
—
—
(4)
TRISB5
T0CS
Bit 5
—
T0IE
RP0
—
—
—
—
(7)
TRISA4
TRISB4
Write Buffer for the upper 5 bits of the Program Counter
T0SE
Bit 4
INTE
TO
—
—
—
TRISA3
TRISB3
RBIE
Bit 3
PSA
PD
—
—
—
TRISA2
TRISB2
CCP1IE
PCFG2
Bit 2
T0IF
PS2
—
Z
TMR2IE
TRISA1
TRISB1
PCFG1
INTF
Bit 1
POR
PS1
DC
© 2007 Microchip Technology Inc.
TMR1IE
TRISA0
TRISB0
PCFG0
Bit 0
RBIF
BOR
PS0
C
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
---0 0000
0000 000x
-0-- -000
---- --qq
1111 1111
---- -000
POR, BOR
Value on
—
—
—
—
35, 52
Page
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