ACE1101BEMT8X Fairchild Semiconductor, ACE1101BEMT8X Datasheet - Page 13

• Manufacturer Part Number: ACE1101BEMT8X
• Description: IC MCU 1KBIT EEPROM 8TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: ACEX® 11xxr

Specifications of ACE1101BEMT8X

• Core Processor: ACE1001
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

ACE1101 Product Family Rev. B.2
The Accumulator is a general-purpose 8-bit register that is used
to hold data and results of arithmetic calculations or data manipu-
lations.
The X-Pointer register allows for an 11-bit indexing value to be
added to an 8-bit offset creating an effective address used for
reading and writing between the entire memory space. (Software
can only read from code EEPROM.) This provides software with the
flexibility of storing lookup tables in the code EEPROM memory
space for the core’s accessibility during normal operation.
The ACEx core allows software to access the entire 11-bit X-
Pointer register using the special X-pointer instructions (e.g. LD X,
#000H). (See Table 9) However, software may also access the
register through any of the memory-mapped instructions using the
XHI (X[10:8]) and XLO (X[7:0]) variables located at 0xBE and
0xBF, respectively. (See Table 11)
The X register is divided into two sections. The 10 least significant
bits (LSB) of the register is the address of the program or data
memory space. The most significant bit (MSB) of the register is
write only and selects between the data (0x000 to 0x0FF) or
program (0xC00 to 0xFFF) memory space.
Example: If Bit 10 = 0, then the LD A, [00,X] instruction will take a
value from address range 0x000 to 0x0FF and load it into A. If Bit
10 = 1, then the LD A, [00,X] instruction will take a value from
address range 0xC00 to 0xFFF and load it into A.
The X register can also serve as a counter or temporary storage
register. However, this is true only for the 10-LSBs since the 11
bit is dedicated for memory space selection.
The 10-bit program counter register contains the address of the
next instruction to be executed. After a reset, if in normal mode the
program counter is initialized to 0xC00.
The ACEx microcontroller has an automatic program stack with a 4-
bit stack pointer. The stack can be initialized to any location between
addresses 0x30-0x3F. Normally, the stack pointer is initialized by one
of the first instructions in an application program. After a reset, the
stack pointer is defaulted to 0xF pointing to address 0x3F.
The stack is configured as a data structure which decrements from
high to low memory. Each time a new address is pushed onto the
stack, the core decrements the stack pointer by two. Each time an
address is pulled from the stack, the core increments the stack
pointer is by two. At any given time, the stack pointer points to the
next free location in the stack.
When a subroutine is called by a jump to subroutine (JSR)
4
3
2
1
th
instruction, the address of the instruction is automatically pushed
onto the stack least significant byte first. When the subroutine is
finished, a return from subroutine (RET) instruction is executed.
The RET instruction pulls the previously stacked return address
from the stack and loads it into the program counter. Execution
then continues at the recovered return address.
This 8-bit register contains four condition code indicators (C, H, Z,
and N), one interrupt masking bit (G), and an EEPROM write flag
(R). In the ACEx microcontroller, condition codes are automati-
cally updated by most instructions. (See Table 10)
The carry flag is set if the arithmetic logic unit (ALU) performs a carry
or borrow during an arithmetic operation and by its dedicated
instructions. The rotate instruction operates with and through the
carry bit to facilitate multiple-word shift operations. The LDC and
INVC instructions facilitate direct bit manipulation using the carry flag.
The half carry flag indicates whether an overflow has taken place on the
boundary between the two nibbles in the accumulator. It is primarily
used for Binary Coded Decimal (BCD) arithmetic calculation.
The zero flag is set if the result of an arithmetic, logic, or data
manipulation operation is zero. Otherwise, it is cleared.
The negative flag is set if the MSB of the result from an arithmetic,
logic, or data manipulation operation is set to one. Otherwise, the
flag is cleared. A result is said to be negative if its MSB is a one.
The interrupt request mask (G) is a global mask that disables all
maskable interrupt sources. If the G Bit is cleared, interrupts can
become pending, but the operation of the core continues uninter-
rupted. However, if the G Bit is set an interrupt is recognized. After any
reset, the G bit is cleared by default and can only be set by a software
instruction. When an interrupt is recognized, the G bit is cleared after
the PC is stacked and the interrupt vector is fetched. Once the interrupt
is serviced, a return from interrupt instruction is normally executed to
restore the PC to the value that was present before the interrupt
occurred. The G bit is reset to one after a return from interrupt is
executed. Although the G bit can be set within an interrupt service
routine, “nesting” interrupts in this way should only be done when there
is a clear understanding of latency and of the arbitration mechanism.
When an interrupt is recognized, the current instruction com-
pletes its execution. The return address (the current value in the
program counter) is pushed onto the stack and execution contin-
MIW
Timer0
Timer1
Software
(EDGEI)
(TMRI0)
(TMRI1)
(INTR)
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