ACE1202LEM8X Fairchild Semiconductor, ACE1202LEM8X Datasheet - Page 34

• Manufacturer Part Number: ACE1202LEM8X
• Description: IC MCU 2KBIT EEPROM 8SOIC
• Manufacturer: Fairchild Semiconductor
• Series: ACEX® 12xxr

Specifications of ACE1202LEM8X

• Core Processor: ACE1202
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

ACE1202 Product Family Rev. B.1
The HALT mode is a power saving feature that almost completely
shuts down the device for current conservation. The device is
placed into HALT mode by setting the HALT enable bit (EHALT)
of the HALT register through software using only the “LD M, #”
instruction. EHALT is a write only bit and is automatically cleared
upon exiting HALT. When entering HALT, the internal oscillator
and all the on-chip systems including the LBD and the BOR
circuits are shut down.
The device can exit HALT mode only by the MIW circuit. There-
fore, prior to entering HALT mode, software must configure the
MIW circuit accordingly. (See Section 9) After a wakeup from
HALT, a 1ms start-up delay is initiated to allow the internal
oscillator to stabilize before normal execution resumes. Immedi-
ately after exiting HALT, software must clear the Power Mode
Clear (PMC) register by only using the “LD M, #” instruction. (See
Figure 36)
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Bit 7
Multi-Input
Wakeup
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Bit 6
LD HALT, #01h
LD PMC, #00h
Normal Mode
Normal Mode
Resume
Halt
33pF
a)
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Bit 5
(G1)
CKI
1M
CKO
(G0)
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33pF
Bit 4
b)
In addition to the HALT mode power saving feature, the device
also supports an IDLE mode operation. The device is placed into
IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT
register through software using only the “LD M, #” instruction.
EIDLE is a write only bit and is automatically cleared upon exiting
IDLE. The IDLE mode operation is similar to HALT except the
internal oscillator, the Watchdog, and the Timer 0 remain active
while the other on-chip systems including the LBD and the BOR
circuits are shut down.
The device automatically wakes from IDLE mode by the Timer 0
overflow every 8192 cycles (see Section 6). Before entering IDLE
mode, software must clear the WKEN register to disable the MIW
block. Once a wake from IDLE mode is triggered, the core will begin
normal operation by the next clock cycle. Immediately after exiting
IDLE mode, software must clear the Power Mode Clear (PMC)
register by using only the "LD M, #" instruction. (See Figure 37)
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C
Bit 3
(G1)
CKI
R
Overflow
Timer 0
CKO
(G0)
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Bit 2
V
CLR WKEN
LD
LD PMC, #00h
Normal Mode
Normal Mode
CC
Resume
IDLE
HALT, #02h
EIDLE
Bit 1
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EHALT
Bit 0