AT87C51RC2-RLTUL Atmel, AT87C51RC2-RLTUL Datasheet - Page 35

• Manufacturer Part Number: AT87C51RC2-RLTUL
• Description: IC 8051 MCU 32K OTP 30MHZ 44VQFP
• Manufacturer: Atmel
• Series: 87Cr

Specifications of AT87C51RC2-RLTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 30/20MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: UART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Figure 6-12. UART Timings in Modes 2 and 3
6.4.2
6.4.3
4188F–8051–01/08
Automatic Address Recognition
Given Address
The automatic address recognition feature is enabled when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor commu-
nication feature by allowing the serial port to examine the address of each incoming command
frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON
register to generate an interrupt. This ensures that the CPU is not interrupted by command
frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configu-
ration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received
command frame address matches the device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broad-
cast address.
Note:
Each device has an individual address that is specified in SADDR register; the SADEN register
is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given
address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The
following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
The following is an example of how to use given addresses to address different slaves:
SMOD0=0
SMOD0=1
SMOD0=1
Slave A:SADDR1111 0001b
Slave B:SADDR1111 0011b
The multiprocessor communication and automatic address recognition features cannot be
enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
SADEN1111 1010b
Given1111 0X0Xb
SADEN1111 1001b
Given1111 0XX1b
RXD
FE
RI
RI
Start
bit
D0
D1
D2
D3
Data byte
D4
D5
D6
D7
AT/TS8xC51Rx2
Ninth
D8
bit
Stop
bit
35