AT87C51RD2-SLSUL Atmel, AT87C51RD2-SLSUL Datasheet - Page 13
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AT87C51RD2-SLSUL
Manufacturer Part Number
AT87C51RD2-SLSUL
Description
IC 8051 MCU 64K OTP 30MHZ 44PLCC
Manufacturer
Atmel
Series
87Cr
Datasheet
1.TS87C51RB2-VIA.pdf
(86 pages)
Specifications of AT87C51RD2-SLSUL
Core Processor
8051
Core Size
8-Bit
Speed
30/20MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Figure 5-2.
4188F–8051–01/08
XTAL1
XTAL1:2
X2 bit
CPU clock
Mode Switching Waveforms
STD Mode
Figure 5-1.
The X2 bit in the CKCON register
tion to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode).
Setting this bit activates the X2 feature (X2 mode).
Note:
Table 5-2.
Bit Number
7
-
7
6
5
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all
peripherals using clock frequency as time reference (UART, timers, PCA...) will have their time ref-
erence divided by two. For example a free running timer generating an interrupt every 20 ms will
then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.
XTAL1
Mnemonic
Clock Generation Diagram
CKCON Register
CKCON - Clock Control Register (8Fh)
6
Bit
-
F
-
-
-
XTAL
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
2
X2 Mode
(Table
XTAL1:2
4
-
5-2) allows to switch from 12 clock cycles per instruc-
CKCON reg
X2
0
1
3
-
F
OSC
AT/TS8xC51Rx2
2
-
CPU control
state machine: 6 clock cycles.
STD Mode
1
-
X2
0
13