AT87C51RD2-SLSUL Atmel, AT87C51RD2-SLSUL Datasheet - Page 61
![IC 8051 MCU 64K OTP 30MHZ 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
AT87C51RD2-SLSUL
Manufacturer Part Number
AT87C51RD2-SLSUL
Description
IC 8051 MCU 64K OTP 30MHZ 44PLCC
Manufacturer
Atmel
Series
87Cr
Datasheet
1.TS87C51RB2-VIA.pdf
(86 pages)
Specifications of AT87C51RD2-SLSUL
Core Processor
8051
Core Size
8-Bit
Speed
30/20MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
4188F–8051–01/08
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
6. Under steady state (non-transient) conditions, I
7. For other values, please contact your sales office.
8. Operating I
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi V
5V.
Maximum I
Maximum I
Port 0: 26 mA
Ports 1, 2, 3 and 4 and 5 when available: 15 mA
Maximum total I
If I
than the listed test conditions.
V
V
would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is
the worst case.
SS
IH
OL
= V
+ 0.5 V,
exceeds the test condition, V
CC
- 0.5V; XTAL2 N.C.; EA = Port 0 = V
OL
OL
CC
per port pin: 10 mA
per 8-bit port:
is measured with all output pins disconnected; XTAL1 driven with T
OL
Figure 11-1. I
Figure 11-2. Operating I
OL
for all output pins: 71 mA
peak 0.6V. A Schmitt Trigger use is not necessary.
Reset = Vss after a high pulse
during at least 24 clock cycles
CC
OL
CLOCK
SIGNAL
CLOCK
SIGNAL
may exceed the related specification. Pins are not guaranteed to sink current greater
Test Condition, under reset
(NC)
(NC)
V
CC
CC
CC
OL
; RST = V
Test Condition
must be externally limited as follows:
RST
XTAL2
XTAL1
V
RST
XTAL2
XTAL1
V
SS
SS
SS
V
V
EA
EA
. The internal ROM runs the code 80 FE (label: SJMP label). I
CC
CC
I
P0
I
P0
CC
CC
V
V
CC
CC
V
V
CC
CC
All other pins are disconnected.
All other pins are disconnected.
CLCH
, T
CHCL
AT/TS8xC51Rx2
= 5 ns (see Figure 11-5.), V
OL
s of ALE and Ports 1
IL
CC
61
=