TS80C32X2-VCED Atmel, TS80C32X2-VCED Datasheet - Page 9

• Manufacturer Part Number: TS80C32X2-VCED
• Description: IC 8051 MCU ROMLESS 5V 44VQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of TS80C32X2-VCED

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60/30MHz
• Connectivity: UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 2. Mode Switching Waveforms
4184G–8051–09/06
XTAL1
XTAL1:2
X2 bit
CPU clock
STD Mode
The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles
per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated
(STD mode). Setting this bit activates the X2 feature (X2 mode).
Note:
Table 3. CKCON Register
CKCON - Clock Control Register (8Fh)
Reset Value = XXXX XXX0b
Not bit addressable
For further details on the X2 feature, please refer to ANM072 available on the web
(http://www.atmel.com)
Number
Bit
7
-
7
6
5
4
3
2
1
0
In order to prevent any incorrect operation while operating in X2 mode, user must be
aware that all peripherals using clock frequency as time reference (UART, timers) will
have their time reference divided by two. For example a free running timer generating an
interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud
rate will have 9600 baud rate.
Mnemonic Description
Bit
X2
6
-
-
-
-
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, F
Set to select 6 clock periods per machine cycle (X2 mode, F
X2 Mode
5
-
4
-
3
-
2
-
STD Mode
TS8xCx2X2
1
OSC
-
=F
OSC
XTAL
=F
).
XTAL
X2
0
/
2).
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