ATTINY44V-10MU Atmel, ATTINY44V-10MU Datasheet - Page 39
![IC MCU AVR 4K FLASH 10MHZ 20-QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY44V-10MU
Manufacturer Part Number
ATTINY44V-10MU
Description
IC MCU AVR 4K FLASH 10MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY44V-10MU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
20MLF
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY44V-10MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 39 of 238
- Download datasheet (5Mb)
8. System Control and Reset
8.1
8006K–AVR–10/10
Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. The circuit diagram in
reset circuitry are given in
Figure 8-1.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in
BODLEVEL [2..0]
Reset Logic
Pull-up Resistor
FILTER
SPIKE
Table 20-4 on page
CKSEL[3:0]
Power-on Reset
Figure 8-1
Reset Circuit
SUT[1:0]
Brown-out
Watchdog
Oscillator
Generator
Circuit
Clock
shows the reset logic. Electrical parameters of the
CK
177.
Register (MCUSR)
MCU Status
DATA BUS
“Clock Sources” on page
Delay Counters
ATtiny24/44/84
TIMEOUT
25.
39
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