ATTINY44V-10SSU Atmel, ATTINY44V-10SSU Datasheet - Page 140

IC MCU AVR 4K FLASH 10MHZ 14SOIC

ATTINY44V-10SSU

Manufacturer Part Number
ATTINY44V-10SSU
Description
IC MCU AVR 4K FLASH 10MHZ 14SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets

Specifications of ATTINY44V-10SSU

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Package
14SOIC
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
12
Interface Type
SPI/USI
On-chip Adc
8-chx10-bit
Number Of Timers
2
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY44V-10SSU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
16.9
16.10 ADC Accuracy Definitions
140
Noise Canceling Techniques
ATtiny24/44/84
Figure 16-8. Analog Input Circuitry
Note:
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. When conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as
described in
is above 1 MHz, or when the ADC is used for reading the internal temperature sensor, as
described in
bypass capacitors does reduce the need for using ADC Noise Reduction Mode
An n-bit single-ended ADC converts a voltage linearly between GND and V
(LSBs). The lowest code is read as 0, and the highest code is read as 2
Several parameters describe the deviation from the ideal behavior, as follows:
• Keep analog signal paths as short as possible.
• Make sure analog tracks run over the analog ground plane.
• Keep analog tracks well away from high-speed switching digital tracks.
• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.
• Place bypass capacitors as close to V
The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and
any stray or parasitic capacitance inside the device. The value given is worst case.
ADCn
Section 16.7 on page
Section 16.12 on page
I
IH
139. This is especially the case when system clock frequency
I
IL
144. A good system design with properly placed, external
CC
and GND pins as possible.
1..100 kohm
C
S/H
= 14 pF
n
-1.
V
CC
REF
/2
8006K–AVR–10/10
in 2
n
steps

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