AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 143
AT91SAM7X128-CU
Manufacturer Part Number
AT91SAM7X128-CU
Description
MCU ARM 128K HS FLASH 100-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7X128-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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22.3.4
22.3.5
6120H–ATARM–17-Feb-09
Data Transfers
Priority of PDC Transfer Requests
Programming the Next Counter/Pointer registers chains the buffers. The counters are decre-
mented after each data transfer as stated above, but when the transfer counter reaches zero,
the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in order to
re-enable the triggers.
For each channel, two status bits indicate the end of the current buffer (ENDRX, ENTX) and the
end of both current and next buffer (RXBUFF, TXBUFE). These bits are directly mapped to the
peripheral status register and can trigger an interrupt request to the AIC.
The peripheral end flag is automatically cleared when one of the counter-registers (Counter or
Next Counter Register) is written.
Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero.
The peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals.
When the peripheral receives an external character, it sends a Receive Ready signal to the PDC
which then requests access to the system bus. When access is granted, the PDC starts a read
of the peripheral Receive Holding Register (RHR) and then triggers a write in the memory.
After each transfer, the relevant PDC memory pointer is incremented and the number of trans-
fers left is decremented. When the memory block size is reached, a signal is sent to the
peripheral and the transfer stops.
The same procedure is followed, in reverse, for transmit transfers.
The Peripheral DMA Controller handles transfer requests from the channel according to priori-
ties fixed for each product.These priorities are defined in the product datasheet.
If simultaneous requests of the same type (receiver or transmitter) occur on identical peripher-
als, the priority is determined by the numbering of the peripherals.
If transfer requests are not simultaneous, they are treated in the order they occurred. Requests
from the receivers are handled first and then followed by transmitter requests.
AT91SAM7X512/256/128 Preliminary
143
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