ADUC831BS Analog Devices Inc, ADUC831BS Datasheet - Page 38

• Manufacturer Part Number: ADUC831BS
• Description: IC ADC/DAC 12BIT W/MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC831BS

• Rohs Status: RoHS non-compliant
• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• For Use With: EVAL-ADUC831QSZ - KIT DEV FOR ADUC831 QUICK START

ADuC831
SERIAL PERIPHERAL INTERFACE
The ADuC831 integrates a complete hardware Serial Peripheral
Interface (SPI) on-chip. SPI is an industry standard synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and received simultaneously, i.e., full duplex.
It should be noted that the SPI pins are shared with the I
interface pins. Therefore, the user can only enable one or the
other interface at any given time (see SPE in Table XI below).
The SPI Port can be configured for Master or Slave operation,
and typically consists of four pins, namely:
MISO (Master In, Slave Out Data I/O Pin)
The MISO (master in slave out) pin is configured as an input
line in master mode and an output line in slave mode. The MISO
line on the master (data in) should be connected to the MISO
line in the slave device (data out). The data is transferred as
byte wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (master out slave in) pin is configured as an output line
in master mode and an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte
wide (8-bit) serial data, MSB first.
SCLOCK (Serial Clock I/O Pin)
The master serial clock (SCLOCK) is used to synchronize the
data being transmitted and received through the MOSI and MISO
SPICON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
The CPOL and CPHA bits should both contain the same values for master and slave devices.
Name
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
SPI Control Register
F8H
OOH
Yes
SPI Interrupt Bit.
Write Collision Error Bit.
SPI Interface Enable Bit.
SPI Master/Slave Mode Select Bit.
Clock Polarity Select Bit.
Clock Phase Select Bit.
SPI Bit-Rate Select Bits.
These bits select the SCLOCK rate (bit-rate) in Master Mode as follows:
Description
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
Set by user to enable the SPI interface.
Cleared by user to enable the I
Set by user to enable Master Mode operation (SCLOCK is an output).
Cleared by user to enable Slave Mode operation (SCLOCK is an input).
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
SPR1
0
0
1
1
In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external SS pin can be read via the SPR0 bit.
Table XI. SPICON SFR Bit Designations
SPR0
0
1
0
1
2
C
Selected Bit Rate
f
f
f
f
OSC
OSC
OSC
OSC
–38–
/2
/4
/8
/16
2
C interface.
data lines. A single data bit is transmitted and received in each
SCLOCK period. Therefore, a byte is transmitted/received
after eight SCLOCK periods. The SCLOCK pin is configured as
an output in master mode and as an input in slave mode. In master
mode the bit-rate, polarity and phase of the clock are controlled by
the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR
(see Table XI). In slave mode the SPICON register will have to
be configured with the phase and polarity (CPHA and CPOL) of
the expected input clock. In both master and slave modes, the data
is transmitted on one edge of the SCLOCK signal and sampled
on the other. It is important therefore, that the CPHA and CPOL
are configured the same for the master and slave devices.
Slave Select Input Pin (SS)
The Slave Select (SS) input pin is shared with the ADC5 input.
In order to configure this pin as a digital input, the bit must be
cleared, e.g., CLR P1.5.
This line is active low. Data is only received or transmitted in slave
mode when the SS pin is low, allowing the ADuC831 to be used
in single master, multislave SPI configurations. If CPHA = 1 then the
SS input may be permanently pulled low. With CPHA = 0, the SS
input must be driven low before the first bit in a byte wide transmis-
sion or reception and return high again after the last bit in that byte
wide transmission or reception. In SPI slave mode, the logic level on
the external SS pin can be read via the SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
REV. 0