LPC2114FBD64,151 NXP Semiconductors, LPC2114FBD64,151 Datasheet - Page 21

• Manufacturer Part Number: LPC2114FBD64,151
• Description: IC ARM7 MCU FLASH 128K 64-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2114FBD64,151

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: MCB2100 - BOARD EVAL NXP LPC211X/LPC212X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 568-1222; 935274514151; LPC2114FBD64-S

NXP Semiconductors
LPC2114_2124_6
Product data sheet
CAUTION
6.17.4 Code security (Code Read Protection - CRP)
6.17.5 External interrupt inputs
6.17.6 Memory mapping control
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
This feature of the LPC2114/2124/01 allows the user to enable different levels of security
in the system so that access to the on-chip flash and use of the JTAG and ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too. It
is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
Remark: Devices without the suffix /00 or /01 have only a security level equivalent to
CRP2 available.
The LPC2114/2124 include up to nine edge or level sensitive External Interrupt Inputs as
selectable pin functions. When the pins are combined, external events can be processed
as four independent interrupt signals. The External Interrupt Inputs can optionally be used
to wake up the processor from Power-down mode.
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
Rev. 06 — 10 December 2007
DD
ramp (in the case of power on), the type of crystal
Single-chip 16/32-bit microcontrollers
LPC2114/2124
© NXP B.V. 2007. All rights reserved.
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