LPC2888FET180,551 NXP Semiconductors, LPC2888FET180,551 Datasheet
LPC2888FET180,551
Specifications of LPC2888FET180,551
935281371551
LPC2888FET180-S
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LPC2888FET180,551 Summary of contents
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LPC2880; LPC2888 16/32-bit ARM microcontrollers cache flash, Hi-Speed USB 2.0 device, and SDRAM memory interface Rev. 03 — 17 April 2008 1. General description The LPC2880/2888 is an ARM7-based microcontroller for portable applications requiring ...
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... NXP Semiconductors I 10-bit ADC with 5-channel input multiplexing I 16-bit stereo ADC and DACs with gain control I Advanced clock generation and power control reduce power consumption I Two 32-bit timers with selectable prescalers I 8-bit/4-bit LCD interface bus I Real-Time Clock (RTC) can be clocked by 32 kHz oscillator or another source ...
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... NXP Semiconductors 4. Block diagram LPC2880/2888 1 MB (1) FLASH SRAM FLASH SRAM INTERFACE INTERFACE +1 DC-TO-DC 3.3 V, CONVERTER 1.8 V START, STOP WATCHDOG SYSTEM CONTROL EVENT ROUTER CLOCK XTALI OSCILLATOR GENERATION AND PLLs XTALO X32I REAL-TIME OSCILLATOR CLOCK X32O GENERAL Px.y PURPOSE I/O 10-BIT A/D ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Pin configuration Table 3. Pin Symbol Row A 1 D0/P0[0] 5 D6/P0[6] 9 RAS/P1[17] 13 A18/P1[2] 17 OE/P1[18] Row B 1 RPO/P1[19] 5 D7/P0[7] 9 DYCS/P1[8] 13 A19/P1[3] 17 A9/P0[25] Row C 1 LD1/P4[5] 5 D9/P0[9] 9 STCS0/P1[5] 13 A20/P1[4] 17 A10/P0[26] Row D 1 LD4/P4[8] LPC2880_LPC2888_3 Preliminary data sheet ...
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... NXP Semiconductors Table 3. Pin Symbol A4/P0[20] Row A1/P0[17] Row DATO/P3[6] Row WSI/P3[2] Row BCKI/P3[1] Row J 1 MD2/P5[ SDA Row K 1 RTS/P6[ P2[1] Row START Row M 1 VREFN(DAC DCDC_V Row DCDC_LX2 Row LPC2880_LPC2888_3 Preliminary data sheet 16/32-bit ARM microcontrollers with external memory interface Pin allocation table … ...
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... NXP Semiconductors Table 3. Pin Symbol 17 DCDC_LX1 Row Row T 1 AINR 5 JTAG_TDI JTAG_TRST 17 DM Row U 1 VREF(DADC) 5 AIN4 JTAG_TDO 17 DP Row V 1 VREFN(DADC XTALO [1] These pins are connected internally and must be left unconnected in an application. 5.2 Pin description Table 4. Pin description Symbol ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball # Type Analog in (single converter) AIN0 U7 I AIN1 T7 I AIN2 U6 I AIN3 T6 I AIN4 V10 P DD(ADC3V3) V U10 P SS(ADC) Analog out (dual channel) AOUTL M2 O AOUTR M3 O VREFN(DAC VREFP(DAC DD(DAC3V3) DAI interface BCKI/P3[1] H17 FI DATI/P3[0] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball # Type External memory interface D0/P0[ D1/P0[1] A2 D2/P0[2] B2 D3/P0[3] A3 D4/P0[4] A4 D5/P0[5] B4 D6/P0[6] A5 D7/P0[7] B5 D8/P0[ D9/P0[9] C5 D10/P0[10] C6 D11/P0[11] B6 D12/P0[12] C7 D13/P0[13] B7 D14/P0[14] C8 D15/P0[15] B8 A0/P0[16] E16 FO A1/P0[17] E17 A2/P0[18] E18 A3/P0[19] D16 A4/P0[20] D17 A5/P0[21] D18 A6/P0[22] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball # Type CKE/P1[9] B10 FO DQM0/P1[10] C12 FO DQM1/P1[11] A11 FO DYCS/P1[ MCLKO/P1[14] A10 FO OE/P1[18] A17 FO RAS/P1[17 RPO/P1[19 STCS0/P1[ STCS1/P1[ STCS2/P1[7] B11 FO WE/P1[15] C11 FO GPIO and mode control MODE1/P2[2] K18 FI MODE2/P2[3] J16 FI P2[0] K16 FI P2[1] K17 C-bus interface ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball # Type Memory card interface MCMD/P5[ MD0/P5[ MD1/P5[ MD2/P5[ MD3/P5[ MCLK/P5[ Oscillator (32.768 kHz) X32I V7 I X32O DD(OSC321V8 SS(OSC32) Oscillator (main) XTALI T10 I XTALO DD(OSC1V8 SS(OSC) Reset RESET T14 I UART CTS/P6[ RXD/P6[ RTS/P6[ TXD/P6[1] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball # Type Digital power and ground DD1(CORE1V8) V V15 P DD1(FLASH1V8) V A16 P DD1(EMC DD1(IO3V3) V V11 P DD2(CORE1V8 DD2(EMC) V V16 P DD2(FLASH1V8 DD2(IO3V3) V V14 P DD3(IO3V3) V J18 P DD4(IO3V3 DD5(IO3V3 DD6(IO3V3 SS1(CORE) V A15 P SS1(EMC) V T12 P SS1(INT SS1(IO) V V12 P SS2(CORE SS2(EMC) V U11 ...
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... NXP Semiconductors Lower speed peripheral functions are connected to the APBs. The four AHB-to-APB bridges interface the APBs to the AHB. 6.1.1 ARM7TDMI processor The ARM7TDMI is a general purpose 32-bit microprocessor that offers high performance and very low power consumption. The ARM architecture is based on RISC principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISCs ...
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... NXP Semiconductors The boot code in this ROM reads the state of the mode inputs and accordingly does one of the following: • Starts execution in internal flash • Starts execution in external memory • Performs a hardware self-test, or • Downloads code from the USB interface into on-chip RAM and transfers control to the downloaded code 6 ...
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... NXP Semiconductors 4.0 GB reserved peripherals includes AHB and 4 APB buses 2.0 GB reserved dynamic memory bank reserved static memory bank external memory (second instance) reserved static memory bank reserved static memory bank 1.0 GB reserved dynamic memory bank reserved static memory bank external memory ...
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... NXP Semiconductors 6.3 Cache The CPU of the LPC2880/2888 has been extended with a 2-way set-associative cache. The cache size and can store both data and instruction code. If code that is being executed is present in the cache from a previous execution, the CPU will not experience code fetch waits. Similarly, if requested data is present in the cache, the CPU will not experience a data access wait ...
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... NXP Semiconductors Programming the flash in a running application is accomplished via a register interface on the APB bus. The flash module can generate an interrupt request when burning or erasing is completed. The flash memory contains a buffer to allow for faster execution. Information is read from the flash 128 bits at a time. The buffer holds this entire amount, which can represent four 32-bit ARM instructions. These captured instructions can them be executed without fl ...
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... NXP Semiconductors – address range with three chip selects. • One chip select for synchronous memory and three chip selects for static memory devices. • Power-saving modes dynamically control CKE and CLKOUT to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • ...
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... NXP Semiconductors 6.9 Event router 88 external and 11 internal LPC2880/2888 signals are connected to the Event Router block. GPIO input pins, functional input pins, and even functional outputs can be monitored by the Event Router. Each signal can act as an interrupt source or a clock-enable for LPC2880/2888 modules, with individual options for high- or low-level sensitivity or rising- or falling-edge sensitivity ...
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... NXP Semiconductors The WDT clock increments a 32-bit Prescale Counter, the value of which is continually compared to the value of the Prescale Register. When the Prescale Counter matches the Prescale Register at a WDT clock edge, the Prescale Counter is cleared and the 32-bit Timer Counter is incremented. Thus the Prescale facility divides the WDT clock by the value in the Prescale Register plus one ...
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... NXP Semiconductors • The GPDMA supports a subset of the flow control signals supported by ARM DMA channels, specifically ‘single’ but not ‘burst’ operation. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • ...
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... NXP Semiconductors • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • Supports normal (100 kHz) and fast (400 kHz) operation. ...
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... NXP Semiconductors The LPC2880/2888 USB controller enables 480 Mbit Mbit/s data exchange with a USB host controller. It includes a USB controller, a DMA engine, and a USB 2.0 ATX physical interface. The USB controller consists of the protocol engine and buffer management blocks. It includes an SRAM that is accessible to the DMA engine and to the processor via the register interface ...
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... NXP Semiconductors 6.20 LCD interface The LCD interface contains logic to interface to a 6800 or 8080 bus compatible LCD controller. The LCD interface is compatible with the 6800 bus standard and the 8080 bus standard, with one address pin (RS) for selecting the data or instruction register. ...
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... NXP Semiconductors The on-chip watchdog timer can cause a chip reset if not updated within a programmable time interval. A status register allows software to determine if a reset was caused by the watchdog timer. The watchdog timer can also be configured to generate an interrupt if desired. Software reset of many individual functional blocks may be performed via registers within the CGU ...
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... NXP Semiconductors 6.21.6 APBs Most peripheral functions are accessed by on-chip APBs that are attached to the higher speed AHB. The APBs perform reads and writes to peripheral registers in three peripheral clocks. 6.22 Emulation and debugging The LPC2880/2888 supports emulation via a dedicated JTAG serial port. The dedicated JTAG port allows debugging of all chip features without impact to any pins that may be used in the application ...
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... NXP Semiconductors 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V external memory controller DD(EMC) supply voltage V analog input voltage IA V input voltage I input voltage I supply current ...
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... NXP Semiconductors 8. Static characteristics Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage (3.3 V) DDA(3V3) V external memory controller DD(EMC) supply voltage Standard pins I LOW-level input current IL I HIGH-level input current ...
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... NXP Semiconductors Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Oscillator pins V crystal input voltage i(xtal) V crystal output voltage o(xtal) DC-to-DC converter V battery supply voltage BAT V DC-to-DC converter 1 output O(DCDC1) voltage I maximum DC-to-DC converter L(DCDC1)(max) 1 load current ...
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... NXP Semiconductors Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Power consumption (battery supplies voltage) I battery supply current BAT Power consumption (DC-to-DC converter supplies voltage) I supply current DD I supply current DD I supply current DD I supply current DD Power consumption (LDO regulator supplies voltage) ...
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... NXP Semiconductors Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter I supply current DD I supply current DD I supply current DD [1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 ˚C), nominal supply voltages. [2] Applies to pins DD1(CORE1V8 DD2(USB1V8) [3] External supply voltage ...
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... NXP Semiconductors 9. Dynamic characteristics Table 7. Dynamic characteristics +85 C, unless otherwise specified. amb Symbol Parameter External clock f external clock frequency ext Port pins t rise time r t fall time f [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Supplied by an external crystal. ...
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... NXP Semiconductors Table 8. Dynamic characteristics: static external memory interface pF amb DD1(EMC) Symbol Parameter Common to read and write cycles t CS LOW to address valid CSLAV time Read cycle parameters t OE LOW to address valid OELAV time t BLS LOW to address valid BLSLAV time t CS LOW to OE LOW time ...
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... NXP Semiconductors Table 9. Dynamic characteristics: dynamic external memory interface pF amb DD1(EMC) Symbol Parameter [1] Read cycle parameters t clock HIGH time CHCX t clock LOW time CLCX T clock cycle time CLCL t chip select set-up time su(S) t chip select hold time h(S) t row address strobe set-up time ...
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... NXP Semiconductors Table 10. Dynamic characteristics: dynamic external memory interface pF amb DD1(EMC) Symbol Parameter [1] Read cycle parameters t clock HIGH time CHCX t clock LOW time CLCX T clock cycle time CLCL t chip select set-up time su(S) t chip select hold time h(S) t row address strobe set-up time ...
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... NXP Semiconductors 9.1 Timing STCS t CSLAV A t OELAV OE t CSLOEL t BLSLAV BLS t CSLBLSL D Fig 4. External memory read access to static memory LPC2880_LPC2888_3 Preliminary data sheet LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface t OELOEH t BLSLBLSH Rev. 03 — 17 April 2008 t CSHOEH t OEHANV ...
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... NXP Semiconductors STCS t CSLAV A t CSLDV D t CSLWEL WE t WELDV t CSLBLSL BLS Fig 5. External memory write access to static memory LPC2880_LPC2888_3 Preliminary data sheet LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface t WELWEH t BLSLBLSH Rev. 03 — 17 April 2008 t BLSHANV t WEHANV t WEHDNV ...
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... NXP Semiconductors CLK DYCS RAS CAS, DQM A D Fig 6. External memory read access to dynamic memory LPC2880_LPC2888_3 Preliminary data sheet 16/32-bit ARM microcontrollers with external memory interface t h(S) t su(S) t h(RAS) t su(RAS h(CAS), h( su(CAS), su(G) t h(A) t su( Rev. 03 — 17 April 2008 LPC2880; LPC2888 ...
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... NXP Semiconductors CLK DYCS RAS WE CAS, DQM A D Fig 7. External memory write access to dynamic memory LPC2880_LPC2888_3 Preliminary data sheet 16/32-bit ARM microcontrollers with external memory interface t h(S) t su(S) t h(RAS) t su(RAS) t h(W) t su( h(CAS), h(DQM su(CAS), su(DQM) t h(A) t su(A) t h(DQ) t su(DQ) Rev. 03 — 17 April 2008 LPC2880 ...
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... NXP Semiconductors 10. Package outline TFBGA180: plastic thin fine-pitch ball grid array package; 180 balls; body 0.8 mm ball A1 index area ball index area 2 4 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.31 0.84 0.39 mm 1.11 0.19 0.76 0.29 OUTLINE VERSION IEC SOT640-1 Fig 8 ...
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... NXP Semiconductors 11. Abbreviations Table 11. Acronym ADC AMBA AHB APB CISC CGU DAC DMA DAI DAO FIQ GPIO IrDA IRQ JTAG LCD MCI PLL RISC SD SD/MMC SDRAM SOF SRAM UART USB WDT LPC2880_LPC2888_3 Preliminary data sheet 16/32-bit ARM microcontrollers with external memory interface ...
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... NXP Semiconductors 12. Revision history Table 12. Revision history Document ID Release date LPC2880_LPC2888_3 20080417 • Modifications: Table 1 “Ordering • Table 2 “Ordering /01 and /D1 devices. • Table • Table • Table • Figure • Figure LPC2880_LPC2888_2 20061121 LPC2880_LPC2888_1 20060622 LPC2880_LPC2888_3 Preliminary data sheet 16/32-bit ARM microcontrollers with external memory interface ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . 11 6.1 Architectural overview 6.1.1 ARM7TDMI processor . . . . . . . . . . . . . . . . . . 12 6.1.2 On-chip flash memory system . . . . . . . . . . . . 12 6 ...