Z86D7308VSC1987 Zilog, Z86D7308VSC1987 Datasheet - Page 63

• Manufacturer Part Number: Z86D7308VSC1987
• Description: IC 32K OTP 3 VOLT 44-PLCC
• Manufacturer: Zilog
• Series: Z8® IRr

Specifications of Z86D7308VSC1987

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PS019401-1102
Power-On Reset (POR)
A timer circuit clocked by a dedicated on-board RC oscillator is used for the
Power-On Reset (POR) timer function. The POR time allows V
tor circuit to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
•
•
•
The POR timer is a nominal 5 ms. Bit 5 of the Stop-Mode Register determines
whether the POR timer is bypassed after Stop-Mode Recovery (typical for external
clock, RC and LC oscillators).
HALT
HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/
timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain
active. The devices are recovered by interrupts, either externally or internally gen-
erated. An interrupt request must be executed (enabled) to exit HALT Mode. After
the interrupt service routine, the program continues from the instruction after the
HALT.
STOP
This instruction turns off the internal clock and external crystal oscillation, thereby
reducing the standby current to 10 A or less. STOP Mode is terminated only by a
reset, such as WDT timeout, POR, SMR, or external reset. This condition causes
the processor to restart the application program at address
enter STOP (or HALT) mode, first flush the instruction pipeline to avoid suspend-
ing execution in mid-instruction. Execute a NOP (Op Code =
before the appropriate sleep instruction, as follows:
or
Power Fail to Power OK status, including Waking up from V
Stop-Mode Recovery (if D5 of SMR = 1)
WDT Timeout
FF
6F
FF
7F
NOP
STOP
NOP
HALT
P
R
E
L
I
; clear the pipeline
; enter STOP Mode
; clear the pipeline
; enter HALT Mode
M
I
N
A
40/44/48-Pin Low-Voltage IR OTP
R
Y
000Ch
FFh
CC
BO
) immediately
. In order to
and the oscilla-
Standby
Z86D73
57