ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 210

• Manufacturer Part Number: ST92F150JDV1QC
• Description: IC MCU 128K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150JDV1QC

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2137

MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
DMA ADDRESS POINTER REGISTER (DAPR)
R241 - Read/Write
Register Page: 9
Reset value: undefined
Bits 7:2 = DAP[7:2]: MSB of DMA address regis-
ter location.
These are the most significant bits of the DMA ad-
dress register location programmable by software.
The DAP2 bit may also be toggled by hardware if
the Timer DMA section for the Compare 0 channel
is configured in Swap mode.
Note: During a DMA transfer with the Register
File, the DAPR is not used; however, in Swap
mode, DAP2 is used to point to the correct table.
Bit 1 = DMA-SRCE: DMA source selection.
This bit is fixed by hardware.
0: DMA source is a Capture on REG0R register
1: DMA destination is a Compare on the CMP0R
Bit 0 = PRG/DAT: DMA memory selection.
This bit is set and cleared by software. It is only
meaningful if DCPR.REG/MEM=0.
0: The ISR register is used to extend the address
1: The DMASR register is used to extend the ad-
210/429
REG/MEM PRG/DAT
DAP7 DAP6 DAP5 DAP4 DAP3 DAP2
9
register
of data transferred by DMA (see MMU chapter).
dress of data transferred by DMA (see MMU
chapter).
7
0
0
1
1
0
1
0
1
ISR register used to address
memory
DMASR register used to address
memory
Register file
Register file
DMA Source/Destination
SRCE
DMA
/DAT
PRG
0
INTERRUPT VECTOR REGISTER (T_IVR)
R242 - Read/Write
Register Page: 9
Reset value: xxxx xxx0
This register is used as a vector, pointing to the
16-bit interrupt vectors in memory which contain
the starting addresses of the three interrupt sub-
routines managed by each timer.
Only one Interrupt Vector Register is available for
each timer, and it is able to manage three interrupt
groups, because the 3 least significant bits are
fixed by hardware depending on the group which
generated the interrupt request.
In order to determine which request generated the
interrupt within a group, the T_FLAGR register can
be used to check the relevant interrupt source.
Bits 7:3 = V[4:0]: MSB of the vector address.
These bits are user programmable and contain the
five most significant bits of the Timer interrupt vec-
tor addresses in memory. In any case, an 8-bit ad-
dress can be used to indicate the Timer interrupt
vector locations, because they are within the first
256 memory locations (see Interrupt and DMA
chapters).
Bits 2:1 = W[1:0]: Vector address bits.
These bits are equivalent to bit 1 and bit 2 of the
Timer interrupt vector addresses in memory. They
are fixed by hardware, depending on the group of
sources which generated the interrupt request as
follows:.
Bit 0 = This bit is forced by hardware to 0.
V4
7
W1
0
0
1
1
V3
W0
0
1
0
1
V2
Overflow/Underflow even interrupt
Not available
Capture event interrupt
Compare event interrupt
V1
Interrupt Source
V0
W1
W0
0
0