ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 240
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ST92F150JDV1QC
Manufacturer Part Number
ST92F150JDV1QC
Description
IC MCU 128K FLASH 100-PQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F150JDV1QC
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
77
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-QFP
Processor Series
ST92F15x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
6 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
5 x 16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit x 10 bit
Case
QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2137
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.2 Transmitter
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
– Set the TE bit to send an idle frame as first trans-
– Access the SCISR register and write the data to
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
This flag generates an interrupt if the TIE bit is set
in the SCICR2 register and the IMI0 bit is set in the
SIMRH register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
240/429
9
and the SCIETPR registers.
mission.
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
ter without overwriting the previous data.
Figure
117).
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the IMI0 bit is set in the SIMRH register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: The TDRE and TC bits are cleared by the
same software sequence.
LIN Transmission
The same procedure has to be applied with the fol-
lowing differences:
– Clear the M bit to configure 8-bit word length
– Set the LINE bit to enter LIN Master mode. In this
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see
As long as the SBK bit is set, the SCI sends break
frames to the TDO pin. After clearing this bit by
software, the SCI inserts a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
Idle Characters
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set, i.e. before writing the next byte in the
SCIDR.
case, setting the SBK bit will send 13 low bits.
Figure
118).
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