Z8F3201AN020EC00TR Zilog, Z8F3201AN020EC00TR Datasheet - Page 107
Z8F3201AN020EC00TR
Manufacturer Part Number
Z8F3201AN020EC00TR
Description
IC ENCORE MCU FLASH 32K 44LQFP
Manufacturer
Zilog
Series
Encore!®r
Datasheet
1.Z8F1601VN020EC.pdf
(246 pages)
Specifications of Z8F3201AN020EC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
44-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
Z8F3201AN020EC00T
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Table 53. UARTx Status 1 Register (UxSTAT1)
Table 54. UARTx Control 0 Register (UxCTL0)
PS017610-0404
RESET
RESET
FIELD
FIELD
ADDR
ADDR
BITS
BITS
R/W
R/W
UARTx Control 0 and Control 1 Registers
TEN
R/W
R
7
0
7
0
Reserved
These bits are reserved and must be 0.
MPRX—Multiprocessor Receive
This status bit is for the receiver and reflects the actual status of the last multiprocessor bit
received. Reading from the UART Data register resets this bit to 0.
The UARTx Control 0 and Control 1 registers (Tables 54 and 55) configure the properties
of the UART’s transmit and receive operations. The UART Control registers must ben be
written while the UART is enabled.
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is
enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
REN
R/W
R
6
6
0
0
CTSE
R/W
R
5
0
5
0
Reserved
PEN
R/W
F44H and F4CH
F42H and F4AH
R
4
4
0
0
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
PSEL
R/W
R
3
0
3
0
SBRK
R/W
R
2
0
2
0
STOP
R/W
R
1
0
1
0
Z8 Encore!
MPRX
LBEN
R/W
R
0
0
0
0
UART
®
89
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