LH7A400N0F000B5 Sharp Microelectronics, LH7A400N0F000B5 Datasheet - Page 28

• Manufacturer Part Number: LH7A400N0F000B5
• Description: IC ARM9 BLUESTREAK MCU 256CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A400N0F000B5

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-CABGA
• Data Bus Width: 32 bit
• Data Ram Size: 80 KB
• Maximum Clock Frequency: 250 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

LH7A400
External Bus Interface
LCD controller and DMA engine access to an external
memory system. The LCD controller has access to an
internal frame buffer in embedded SRAM and an exten-
sion buffer in Synchronous Memory for large displays.
The processor and DMA engine share the main system
bus, providing access to all external memory devices
and the embedded SRAM frame buffer.
External Bus Interface (EBI) is only granted when an
existing access has been completed. See Figure 5.
Embedded SRAM
LH7A400 is 80KB. This Embedded memory is designed
to be used for storing code, data, or LCD frame data
and to be contiguous with external SDRAM. The 80KB
is large enough to store a QVGA panel (320 × 240) at 8
bits per pixel, equivalent to 70KB of information.
overall power consumed in any application that uses
the LH7A400. Normally, the system has to perform
external accesses to acquire this data. The LCD con-
troller is designed to automatically use an overflow
frame buffer in SDRAM if a larger screen size is
required. This overflow buffer can be located on any
4KB page boundary in SDRAM, allowing software to
28
The external bus interface allows the ARM922T,
An arbitration unit ensures that control over the
The amount of Embedded SRAM contained in the
Containing the frame buffer on chip reduces the
E000.0000
D000.0000
C000.0000
B001.4000
B000.0000
F000.0000
8000.3800
8000.2000
8000.0000
7000.0000
6000.0000
5000.0000
4000.0000
3000.0000
2000.0000
1000.0000
0000.0000
AHB INTERNAL REGISTERS
APB INTERNAL REGISTERS
ASYNCHRONOUS MEMORY (nCS0)
SYNCHRONOUS MEMORY (nSCS2)
SYNCHRONOUS MEMORY (nSCS1)
SYNCHRONOUS MEMORY (nSCS0)
RESERVED
EMBEDDED SRAM
RESERVED
ASYNCHRONOUS MEMORY (CS7)
ASYNCHRONOUS MEMORY (CS6)
PCMCIA/CompactFlash (nPCSLOTE2)
PCMCIA/CompactFlash (nPCSLOTE1)
ASYNCHRONOUS MEMORY (nCS3)
ASYNCHRONOUS MEMORY (nCS2)
ASYNCHRONOUS MEMORY (nCS1)
SYNCHRONOUS ROM (nSCS3)
SYNCHRONOUS MEMORY BOOT
Figure 4. Memory Mapping for Each Boot Mode
Version 1.0
set the MMU (in the LCD controller) page tables such
that the two memory areas appear contiguous. Byte,
Half-Word and Word accesses are permissible.
Asynchronous Memory Controller
rated as part of the memory controller to provide an
interface between the AMBA AHB system bus and
external (off-chip) memory devices.
port for up to eight independently configurable memory
banks simultaneously. Each memory bank is capable
of supporting:
• SRAM
• ROM
• Flash EPROM
• Burst ROM memory.
16-, or 32-bit external memory data paths. The memory
controller can be configured to support either little-
endian or big-endian operation.
• Non-burst read and write accesses only to high-
• Non-burst write accesses, nonburst read accesses
AHB INTERNAL REGISTERS
APB INTERNAL REGISTERS
speed CMOS static RAM.
and asynchronous page mode read accesses to
fast-boot block flash memory.
SYNCHRONOUS MEMORY (nSCS3)
SYNCHRONOUS MEMORY (nSCS2)
SYNCHRONOUS MEMORY (nSCS1)
SYNCHRONOUS MEMORY (nSCS0)
RESERVED
EMBEDDED SRAM
RESERVED
ASYNCHRONOUS MEMORY (CS7)
ASYNCHRONOUS MEMORY (CS6)
PCMCIA/CompactFlash (nPCSLOTE2)
PCMCIA/CompactFlash (nPCSLOTE1)
ASYNCHRONOUS MEMORY (nCS3)
ASYNCHRONOUS MEMORY (nCS2)
ASYNCHRONOUS MEMORY (nCS1)
ASYNCHRONOUS ROM (nCS0)
The Asynchronous memory controller is incorpo-
The Asynchronous Memory Controller provides sup-
Each memory bank may use devices using either 8-,
The memory banks can be configured to support:
ASYNCHRONOUS MEMORY BOOT
32-Bit System-on-Chip
256MB
256MB
256MB
256MB
80KB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
LH7A400-6
Data Sheet