LH7A400N0F000B5 Sharp Microelectronics, LH7A400N0F000B5 Datasheet - Page 50

• Manufacturer Part Number: LH7A400N0F000B5
• Description: IC ARM9 BLUESTREAK MCU 256CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A400N0F000B5

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-CABGA
• Data Bus Width: 32 bit
• Data Ram Size: 80 KB
• Maximum Clock Frequency: 250 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

LH7A400
Clock and State Controller (CSC)
Waveforms
coming out of Reset or Power On. Figure 22 shows exter-
nal reset timing, and Table 11 gives the timing parame-
ters. Figure 23 depicts signal timing following a Reset. On
transition from Standby to Run (including a Cold Boot),
the Wakeup pin must not be asserted for 2 seconds after
assertion of nPOR to allow time for sampling BATOK and
nEXTPWR. The delay prevents a false ‘battery good’ indi-
cation caused by alkaline battery recovery that can imme-
diately follow a battery-low switch off. The battery
NOTE: *VDDC = VDDCmin
50
tOSC32
tPORH
tOSC14
tPLLL
tURESET/tPWRFL
Figure 21 shows the behavior of the LH7A400 when
PARAMETER
XTAL32
XTAL14
VDDC
nPOR
nURESET
nPWRFL
VDDCmin
32.768 kHz Oscillator Stabilization Time after Power On*
nPOR Hold Time after tOSC32
14.7456 MHz Oscillator Stabilization Time after Wake UP
Phase Locked Loop Lockup Time
nURESET/nPWRFL Pulse Width (once sampled LOW)
tOSC14
tOSC32
Figure 21. Oscillator Start-up
DESCRIPTION
Table 11. Reset AC Timing
Figure 22. External Reset
tPORH
tURESET
tPWRFL
Version 1.0
sampling takes place on the rising edge of the 1 Hz clock.
This clock is derived from the 32.768 kHz oscillator.
The WAKEUP pin can be pulsed, but at least one edge
must follow the 2 second delay to be recognized. For
more information, see the application note “Implementing
Auto-Wakeup on the LH7A4xx Series Devices” at
www.sharpsma.com.
the SHARP LH7A400 32.768 kHz external oscillator
circuit. Figure 25 shows the same for the 14.7456 MHz
external oscillator circuit. In both figures, the NAND
gate represents the internal logic of the chip.
Figure 24 shows the recommended components for
MIN.
0
2
MAX.
550
250
4
32-Bit System-on-Chip
System Clock Cycles
UNIT
ms
ms
ms
µs
Data Sheet
LH7A400-25
LH7A400-26