UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 69
UPSD3433E-40U6
Manufacturer Part Number
UPSD3433E-40U6
Description
MCU 8BIT 8032 128KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3422EV-40U6.pdf
(300 pages)
Specifications of UPSD3433E-40U6
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4907
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPSD3433E-40U6
Manufacturer:
DENSO
Quantity:
83
Company:
Part Number:
UPSD3433E-40U6
Manufacturer:
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UPSD3422, UPSD3433, UPSD3434, UPSD3454
14.2.2
USB_CLK
The UPSD34xx has a dedicated analog phase locked loop (PLL) that can be configured to
generate the 48MHz USB_CLK clock on a wide range of f
must be at 48MHz for the USB to function properly.
The PLL is enabled after power up. The power on lock time for the PLL clock is about 200µs,
and the firmware should wait that much time before enabling the USB_CLK by setting the
UPLLCE Bit in the CCON0 register to '1.' The PLL is disabled in Power-down mode, it can
also be disabled or enabled by writing to the PLLEN Bit in the CCON0 register.
The PLL output clock frequency (f
formula:
where PLLM and PLLD are the multiplier and divisor that are specified in the CCON1
register. The f
generate a stable USB_CLK:
The USB requires a 48MHz clock to operate correctly. The PLLM[4:0] and PLLD[3:0] values
must be selected so as to generate a USB_CLK that is as close to 48MHz as possible at
different oscillator frequencies (f
can be used on common f
Table 26.
a)
b)
c)
(MHz)
f
40.0
36.0
33.0
30.0
24.0
16.0
12.0
OSC
8.0
6.0
3.0
–1 ≤ PLLM ≤ 30 (binary: [11111] ≤ PLLM[4:0] ≤ [11110]),
–1 ≤ PLLD ≤ 14 (binary: [1111] ≤ PLLD[3:0] ≤ [1110]), and
f
OSC
f
USBCLK
PLLM and PLLD values for different f
OSC
/(PLLD+2) must be equal to or greater than 3MHz.
, the PLLM and PLLD range must meet the following conditions to
decimal
=
22
30
14
18
28
30
22
30
30
[
6
[
f
OSC
(
PLLD
PLLM[4:0]
OSC
×
(
+
PLLM
frequencies.
2
OSC
)
USB_CLK
×
binary
10110
00110
11110
01110
10010
11100
11110
10110
11110
11110
).
2
+
]
Table 26
2
)
]
⁄
) can be determined by using the following
lists some of the PLLM and PLLD values that
decimal
–1
OSC
8
1
9
3
3
3
2
0
0
PLLD[3:0]
frequencies
OSC
frequencies. The USB_CLK
binary
1000
0001
1001
0011
0011
0011
0010
0000
0000
1111
MCU clock generation
f
USB_CLK
(MHz)
48.0
48.0
48.0
48.0
48.0
48.0
48.0
48.0
48.0
48.0
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